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Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy

Autor
Aymerich, N.; Rubio, A.
Tipus d'activitat
Article en revista
Revista
Microprocessors and microsystems
Data de publicació
2012-07
Volum
36
Número
5
Pàgina inicial
420
Pàgina final
426
DOI
https://doi.org/10.1016/j.micpro.2012.02.003 Obrir en finestra nova
Projecte finançador
TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS
Repositori
http://hdl.handle.net/2117/16281 Obrir en finestra nova
URL
http://dx.doi.org/10.1016/j.micpro.2012.02.003 Obrir en finestra nova
Resum
One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS and new emerging research devices. The worldwide-accepted predictions with these technologies indicate a remarkable reduction of the components quality, because of the manufacturing process complexity and the erratic behavior of devices, causing a drop in the system reliability i...
Citació
Aymerich, N.; Rubio, J.A. Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy. "Microprocessors and microsystems", Juliol 2012, vol. 36, núm. 5, p. 420-426.
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

Participants