The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13 nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells and circuits.
Canal, R. [et al.]. TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies. "Procedia Computer Science", 22 Desembre 2011, vol. 7, p. 148-149.