Carregant...
Carregant...

Vés al contingut (premeu Retorn)

Circuit design of a dual-versioning L1 data cache

Autor
Seyedi, A.; Armejach, A.; Cristal, A.; Unsal, O.; Hur, I.; Valero, M.
Tipus d'activitat
Article en revista
Revista
Integration. The VLSI journal
Data de publicació
2012-06
Volum
45
Número
3
Pàgina inicial
237
Pàgina final
245
DOI
https://doi.org/10.1016/j.vlsi.2011.11.015 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S0167926011001040 Obrir en finestra nova
Resum
This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors that implement optimistic concurrency proposals. In this cache architecture, each dvSRAM cell has two cells, a main cell and a secondary cell, which keep two versions of the same logical data. These values can be accessed, modified, moved back and forth between the main and secondary cells within the access time of the cache. We design and simulate a 32 KB dual-versioning L1 data c...
Paraules clau
Access Time, Cache Architecture, Circuit Designs, Data Caches, Dual-versioning, Logical Data, Multi-processors, Optimistic Concurrency, Parallelism, Secondary Cells, Sram Cell
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants