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Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations

Autor
Jaksic, Z.; Canal, R.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on electron devices
Data de publicació
2012-12
Volum
60
Número
1
Pàgina inicial
49
Pàgina final
55
DOI
https://doi.org/10.1109/TED.2012.2226095 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/19931 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06374661 Obrir en finestra nova
Resum
We explore the 6T and 8T SRAM design spaces through read static noise margin (RSNM), word-line write margin, and leakage for future 10-nm FinFETs. Process variations are based on the ITRS and modeled at device (TCAD) level. We propose a method to incorporate them into a BSIM-CMG model card for time-efficient simulation. We analyze cells with different fin numbers, supply voltages, and temperatures. Results show a 1.8× improvement of RSNM for 8T SRAM cells, the need for stronger pull-downs to se...
Citació
Jaksic, Z.; Canal, R. Comparison of SRAM cells for 10-nm SOI FinFETs under process and environmental variations. "IEEE transactions on electron devices", Desembre 2012, vol. 60, núm. 1, p. 49-55.
Paraules clau
6T cell, 8T cell, FinFET, SRAM, leakage, process variation
Grup de recerca
VIRTUOS - Virtualisation and Operating Systems

Participants