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Memory controller-level extensions for GDDR5 single device data correct support

Autor
Carretero, J.; Hernández, I.; Vera, F.J.; Juan, A.; Herrero, E.; Ramirez, T.; Monchiero, M.; Gonzalez, A.; Axelos, N.; Sanchez, D.
Tipus d'activitat
Article en revista
Revista
Intel technology journal
Data de publicació
2013-05-01
Volum
17
Número
1
Pàgina inicial
102
Pàgina final
116
URL
http://www.csit-sun.pub.ro/~cpop/Documentatie_SM/Intel_Microprocessor_Systems/Intel%20TechnologyNew/intelr_technology_journal__volume_17_issue_1_2013.pdf Obrir en finestra nova
Resum
Support for Reliability, Availability, and Serviceability (RAS) is one of the quintessential features of computing systems targeting the server and mission-critical markets. Among these RAS features, Chipkill* stands out as the most crucial for main memory protection. IBM Chipkill protects the main memory from the failure of an entire memory chip, as well as multi-bit faults from any portion of a memory chip. Similar technologies from other vendors are Single Device Data Correction (SDDC) from I...
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants