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Measurements of process variability in 40-nm regular and nonregular layouts

Autor
Mauricio, J.; Moll, F.; Gomez, S.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on electron devices
Data de publicació
2014-02-01
Volum
61
Número
2
Pàgina inicial
365
Pàgina final
371
DOI
https://doi.org/10.1109/TED.2013.2294742 Obrir en finestra nova
Projecte finançador
Design And Test Principles For Terascale Integrated Systems
PRINCIPIOS DE DISEÑO Y TEST DE SISTEMAS INTEGRADOS EN TERA-ESCALA
Repositori
http://hdl.handle.net/2117/22068 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6691935 Obrir en finestra nova
Resum
As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a ...
Citació
Mauricio, J.; Moll, F.; Gomez, S. Measurements of process variability in 40-nm regular and nonregular layouts. "IEEE transactions on electron devices", 01 Febrer 2014, vol. 61, núm. 2, p. 365-371.
Paraules clau
Fluctuations, Lithography distortion, Mosfets, Variability
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

Participants