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All-digital simple clock synthesis through a glitch-free variable-length ring oscillator

Autor
Perez, J.; Moll, F.; Calomarde, A.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on circuits and systems II: express briefs
Data de publicació
2014-02-01
Volum
61
Número
2
Pàgina inicial
90
Pàgina final
94
DOI
https://doi.org/10.1109/TCSII.2014.2299096 Obrir en finestra nova
Projecte finançador
Design And Test Principles For Terascale Integrated Systems
PRINCIPIOS DE DISEÑO Y TEST DE SISTEMAS INTEGRADOS EN TERA-ESCALA
Repositori
http://hdl.handle.net/2117/24765 Obrir en finestra nova
Resum
This brief presents a simple all-digital variable-length ring oscillator (VLRO) design that is capable of synchronously changing the output frequency while keeping a signal free of glitches or spurious oscillations at the frequency transitions. The correct operation of the proposed VLRO has been experimentally validated on a 90-nm Xilinx Spartan-3E field-programmable gate array, showing the ability to switch between 16 different frequencies (from 24.1 to 321 MHz for the nominal core supply volta...
Citació
Perez, J.; Moll, F.; Calomarde, A. All-digital simple clock synthesis through a glitch-free variable-length ring oscillator. "IEEE transactions on circuits and systems II: express briefs", 01 Febrer 2014, vol. 61, núm. 2, p. 90-94.
Paraules clau
Clocks, DELAY-LINE, DESIGN, OPERATION, digital circuits, digital integrated circuits, field programmable gate arrays, ring oscillators, semiconductor device reliability
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

Participants