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Hardware-software coherence protocol for the coexistence of caches and local memories

Autor
Alvarez, L.; Vilanova, L.; Gonzalez, M.; Martorell, X.; Navarro, N.; Ayguade, E.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on computers
Data de publicació
2015-01-01
Volum
64
Número
1
Pàgina inicial
152
Pàgina final
165
DOI
https://doi.org/10.1109/TC.2013.194 Obrir en finestra nova
Projecte finançador
Computación de altas prestaciones V: arquitecturas, compiladores, sistemas operativos, herramientas y aplicaciones
Repositori
http://hdl.handle.net/2117/28300 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6616543 Obrir en finestra nova
Resum
Cache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce a local memory alongside the cache hierarchy, forming a hybrid memory system. Local memories are more power-efficient than caches and do not generate coherence traffic, but they suffer from poor programmability. When non-predictable memory access patterns are found, compilers d...
Citació
Álvarez, L. [et al.]. Hardware-software coherence protocol for the coexistence of caches and local memories. "IEEE transactions on computers", 01 Gener 2015, vol. 64, núm. 1, p. 152-165.
Paraules clau
Architecture, Coherence protocol, Efficient, Hybrid memory system, Lcal memories, Performance, Scratchpad memories, Systems
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

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