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Network aware performance evaluation of prefetching techniques in CMPs

Autor
Torrents, M.; Martinez Morais, Raul; Molina, C.
Tipus d'activitat
Article en revista
Revista
Simulation modelling practice and theory
Data de publicació
2014-06-01
Volum
45
Pàgina inicial
1
Pàgina final
17
DOI
https://doi.org/10.1016/j.simpat.2014.03.005 Obrir en finestra nova
Projecte finançador
MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II
Microarquitectura i compiladors (ARCO)
Repositori
http://hdl.handle.net/2117/23050 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S1569190X14000434 Obrir en finestra nova
Resum
This study focuses on the importance of quantifying the effect of prefetching on the interconnection network of a multiprocessor chip. This kind of microarchitectural effects are often quantified using simulators. However, if prefetching traffic in a CMP (Chip MultiProcessor) system is to be accurately evaluated, simulators should simulate not only the memory hierarchy module and the multicore system, but also the network-on-chip. Unfortunately, no open-source simulator is able to evaluate all t...
Citació
Torrents, M.; Martinez Morais, Raul; Molina, C. Network aware performance evaluation of prefetching techniques in CMPs. "Simulation modelling practice and theory", 01 Juny 2014, vol. 45, p. 1-17.
Paraules clau
Cache coherence protocol, Gem5, Multicore, Network-on-chip, Prefetching, Simulation infrastructure
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants

  • Torrents Lapuerta, Marti  (autor)
  • Martinez Morais, Raul  (autor)
  • Molina Clemente, Carlos Maria  (autor)