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Analyzing the efficiency of L1 caches for reliable hybrid-voltage operation using EDC codes

Autor
Maric, B.; Abella, J.; Valero, M.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on very large scale integration (VLSI) systems
Data de publicació
2014-10-01
Volum
22
Número
10
Pàgina inicial
2211
Pàgina final
2215
DOI
https://doi.org/10.1109/TVLSI.2013.2282498 Obrir en finestra nova
Projecte finançador
Computación de Altas Prestaciones VI
URL
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6617723 Obrir en finestra nova
Resum
The increasing demand for highly miniaturized battery-powered ultralow cost systems (e.g., below 1 dollar) in emerging applications such as body, urban life and environment monitoring, and so on, has introduced many challenges in chip design. Such applications require high performance occasionally and very little energy consumption during most of the time to extend battery lifetime. In addition, they require real-time guarantees. Caches have been shown to be the most critical blocks in these sys...
Paraules clau
Caches, Embedded Real-time, Low Energy, Performance Guarantees, Reliability, Subthreshold Sram, Systems
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

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