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Lithography yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations

Autor
Gomez, S.; Moll, F.; Mauricio, J.
Tipus d'activitat
Article en revista
Revista
Proceedings of SPIE, the International Society for Optical Engineering
Data de publicació
2014-02
Volum
9053
Pàgina inicial
90530M-1
Pàgina final
90530M-15
DOI
https://doi.org/10.1117/12.2046208 Obrir en finestra nova
Projecte finançador
Design And Test Principles For Terascale Integrated Systems
SYNTHESIS USING ADVANCED PROCESS TECHNOLOGY INTEGRATED IN REGULAR CELLS, IPS, ARCHITECTURES,
URL
http://spie.org/Publications/Proceedings/Paper/10.1117/12.2046208 Obrir en finestra nova
Resum
A yield estimation model to evaluate the lithography distortion in a printed layout is presented. The yield model relates the probability of non-failure of a lithography hotspot with the manufacturing yield loss. We define a lithography hotspot as a pattern construct with excessive variation under lithography printing using lithography simulations. Thereby, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho-degradation. The appl...
Paraules clau
Design for manufacturability, Layout design, Lithography hotspots, Yield estimation
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

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