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Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations

Autor
Gomez, S.; Moll, F.; Mauricio, J.
Tipus d'activitat
Article en revista
Revista
Journal of micro/nanolithography, MEMS and MOEMS
Data de publicació
2014-07-01
Volum
13
Número
3
DOI
https://doi.org/10.1117/1.JMM.13.3.033016 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/26792 Obrir en finestra nova
URL
http://nanolithography.spiedigitallibrary.org/article.aspx?articleid=1906672 Obrir en finestra nova
Resum
A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yie...
Citació
Gomez, S.; Moll, F.; Mauricio, J. Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations. "Journal of micro/nanolithography, MEMS and MOEMS", 01 Juliol 2014, vol. 13, núm. 3.
Paraules clau
Design for manufacturability, Layout design, Lithography hotspots, Yield estimation
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

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