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Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm

Autor
Amat, Esteve; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, A.
Tipus d'activitat
Article en revista
Revista
Microelectronics journal
Data de publicació
2014-10-01
Volum
45
Número
10
Pàgina inicial
1342
Pàgina final
1347
DOI
https://doi.org/10.1016/j.mejo.2013.12.001 Obrir en finestra nova
Projecte finançador
Design And Test Principles For Terascale Integrated Systems
MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES II
PRINCIPIOS DE DISEÑO Y TEST DE SISTEMAS INTEGRADOS EN TERA-ESCALA
Repositori
http://hdl.handle.net/2117/115934 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S0026269213002930 Obrir en finestra nova
Resum
3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing ...
Citació
Amat, E., García, C., Aymerich, N., Canal, R., Rubio, A. Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm. "Microelectronics journal", 1 Octubre 2014, vol. 45, núm. 10, p. 1342-1347.
Paraules clau
CACHE, CMOS, DESIGN, DRAM, Temperature, Variability
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
VIRTUOS - Virtualisation and Operating Systems

Participants

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