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Efficient power gating of SIMD accelerators through dynamic selective devectorization in an HW/SW codesigned environment

Autor
Kumar, R.; Martinez, A.; Gonzalez, A.
Tipus d'activitat
Article en revista
Revista
ACM transactions on architecture and code optimization
Data de publicació
2014-10-01
Volum
11
Número
3
Pàgina inicial
25:1
Pàgina final
25:23
DOI
https://doi.org/10.1145/2629681 Obrir en finestra nova
Resum
Leakage energy is a growing concern in current and future microprocessors. Functional units of microprocessors are responsible for a major fraction of this energy Therefore, reducing functional unit leakage has received much attention in recent years. Power gating is one of the most widely used techniques to minimize leakage energy. Power gating turns off the functional units during the idle periods to reduce the leakage. Therefore, the amount of leakage energy savings is directly proportional t...
Paraules clau
Algorithms, Devectorization, Experimentation, Hardware/software codesigned processors, Leakage, Performance, Power gating
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants