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Efficient cache designs for probabilistically analysable real-time systems

Autor
Kosmidis, L.; Abella, J.; Quiñones, E.; Cazorla, F. J.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on computers
Data de publicació
2014-12-01
Volum
63
Número
12
Pàgina inicial
2998
Pàgina final
3011
DOI
https://doi.org/10.1109/TC.2013.182 Obrir en finestra nova
Projecte finançador
Computación de Altas Prestaciones VI
URL
http://www.computer.org/csdl/trans/tc/2014/12/06596489-abs.html Obrir en finestra nova
Resum
The increasing performance demand in the critical real-time embedded systems (CRTES) domain calls for high-performance features such as cache memories. Unfortunately, the cost to provide trustworthy and tight Worst-Case Execution Time (WCET) estimates in the presence of caches is high with current practice WCET analysis tools, because they need detailed knowledge of program's cache accesses to provide tight WCET estimates. The advent of Probabilistic timing analysis (PTA) opens the door to econo...
Paraules clau
Cache memories, Execution, Worst-case analysis

Participants

  • Kosmidis, Leonidas  (autor)
  • Abella Ferrer, Jaume  (autor)
  • Quiñones Moreno, Eduardo  (autor)
  • Cazorla Almeida, Francisco Javier  (autor)