Carregant...
Carregant...

Vés al contingut (premeu Retorn)

Analysis of the degradation of HfO2/SiO2 gate stacks using nanoscale and device level techniques

Autor
Aguilera, L.; Amat, Esteve; Rodríguez, R.; Porti, M.; Nafría, M.; Aymerich , X.
Tipus d'activitat
Article en revista
Revista
Microelectronic engineering
Data de publicació
2007
Volum
84
Pàgina inicial
1618
Pàgina final
1621
DOI
https://doi.org/10.1016/j.mee.2007.01.238 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S0167931707002298 Obrir en finestra nova
Resum
In this work, standard device level and nanoscale electrical tests have been carried out to evaluate the influence of the high-k and interfacial SiO2 layers on the degradation of HfO2/SiO2 gate stacks. At device level, the effect of static and dynamic electrical stresses has been investigated to evaluate the influence of the voltage polarity in the degradation of the gate stack. At nanoscale level, a Conductive Atomic Force Microscope (C-AFM) has allowed to separately investigate the effect of t...
Paraules clau
CMOS, Dielectric breakdown, High-k, Oxide reliability

Participants

  • Aguilera, Lidia  (autor)
  • Amat Bertran, Esteve  (autor)
  • Rodríguez Martínez, Rosana  (autor)
  • Porti Pujal, Marc  (autor)
  • Nafría Maqueda, Montserrat  (autor)
  • Aymerich Humet, Xavier  (autor)