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SPICE modelling of hot-carrier degradation in Si1-xGex S/D and HfSiON based pMOS transistors

Autor
Martin, J.; Amat, Esteve; Gonzalez, M.B.; Verheyen, P.; Rodríguez, R.; Nafría, M.; Aymerich , X.; Simoen, E.
Tipus d'activitat
Article en revista
Revista
Microelectronics reliability
Data de publicació
2010
Pàgina inicial
1263
Pàgina final
1266
DOI
https://doi.org/10.1016/j.microrel.2010.07.150 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S0026271410004233 Obrir en finestra nova
Resum
Hot-carrier degradation in pMOS transistors with Si1–xGex implantations in the source and drain areas is analyzed (SiGe S/D). A simulation methodology is developed to translate the effects to circuit simulators. This methodology is applied to study hot-carrier degradation in CMOS inverters designed with SiGe S/D pMOS transistors. The results show that although pMOS transistors with embedded SiGe S/D have a better device performance, these devices are more sensitive to hot-carrier degradation a...

Participants

  • Martin Martínez, Javier  (autor)
  • Amat Bertran, Esteve  (autor)
  • Gonzalez, Mireia B.  (autor)
  • Verheyen, Peter  (autor)
  • Rodríguez Martínez, Rosana  (autor)
  • Nafría Maqueda, Montserrat  (autor)
  • Aymerich Humet, Xavier  (autor)
  • Simoen, Eddy  (autor)