Carregant...
Carregant...

Vés al contingut (premeu Retorn)

Gate voltage influence on the channel hot-carrier degradation of high-k based devices

Autor
Amat, Esteve; Kauerauf, T.; Degraeve, R.; Rodríguez, R.; Nafría, M.; Aymerich , X.; Groeseneken, G.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on device and materials reliability
Data de publicació
2011
Volum
11
Número
1
Pàgina inicial
92
Pàgina final
97
DOI
https://doi.org/10.1109/TDMR.2010.2093138 Obrir en finestra nova
Resum
In ultrascaled complimentary metal–oxide–semiconductor technologies, the lucky-electron model does not describe correctly Channel Hot-Carrier (CHC) degradation for typical transistor test conditions independently of the gate dielectric (SiO2 or high-k). A new model to describe the CHC degradation behavior in n-channel metal–oxide field-effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented. This new model can be applicable to long- and sh...
Paraules clau
High-k, hot carriers, reliability

Participants

  • Amat Bertran, Esteve  (autor)
  • Kauerauf, Thomas  (autor)
  • Degraeve, Robin  (autor)
  • Rodríguez Martínez, Rosana  (autor)
  • Nafría Maqueda, Montserrat  (autor)
  • Aymerich Humet, Xavier  (autor)
  • Groeseneken, Guido  (autor)