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Adaptive Proactive Reconfiguration: A Technique for Process-Variability-and Aging-Aware SRAM Cache Design

Autor
Pouyan, P.; Amat, Esteve; Rubio, A.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on very large scale integration (VLSI) systems
Data de publicació
2015-09-01
Volum
23
Número
9
Pàgina inicial
1951
Pàgina final
1955
DOI
https://doi.org/10.1109/TVLSI.2014.2355873 Obrir en finestra nova
Projecte finançador
Design And Test Principles For Terascale Integrated Systems
PRINCIPIOS DE DISEÑO Y TEST DE SISTEMAS INTEGRADOS EN TERA-ESCALA
Principios de diseño y test de sistemas integrados en tera-escala
Terascale Reliable Adaptive Memory System
Repositori
http://hdl.handle.net/2117/25262 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/document/6915734/ Obrir en finestra nova
Resum
Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive reconfiguration is an emerging technique oriented to extend the system lifetime of memories affected by aging. In this brief, we present a new approach for static random access memory (SRAM) design that extends the cache lifetime when considering process variation and aging in the...
Citació
Pouyan, P.; Amat, Esteve; Rubio, A. Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design. "IEEE transactions on very large scale integration (VLSI) systems", 2014.
Paraules clau
Adaptive proactive reconfiguration, REDUNDANCY, aging sensor, process variation, reliability, static random access memory (SRAM)
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

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