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Hybrid cache designs for reliable hybrid high and ultra-low voltage operation

Autor
Maric, B.; Abella, J.; Cazorla, F. J.; Valero, M.
Tipus d'activitat
Article en revista
Revista
ACM transactions on design automation of electronic systems
Data de publicació
2014-11-01
Volum
20
Número
1
Pàgina inicial
Article No. 10
DOI
https://doi.org/10.1145/2658988 Obrir en finestra nova
Projecte finançador
Computación de Altas Prestaciones VI
URL
http://dl.acm.org/citation.cfm?id=2690851.2658988&coll=DL&dl=ACM&CFID=619558704&CFTOKEN=44653771 Obrir en finestra nova
Resum
Geometry scaling of semiconductor devices enables the design of ultra-low-cost (e.g., below 1 USD) battery-powered resource-constrained ubiquitous devices for environment, urban life, and body monitoring. These sensor-based devices require high performance to react in front of infrequent particular events as well as extreme energy efficiency in order to extend battery lifetime during most of the time when low performance is required. In addition, they require real-time guarantees. The most suita...
Paraules clau
Architecture, Behavior, CMOS, Cache memories, Design, Efficient, Embedded real time, Hybrid voltage operation, Low energy, Memory, Performance, Power, Processor, Reliability, SRAM design, Sensor network, Systems
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Maric, Bojan  (autor)
  • Abella Ferrer, Jaume  (autor)
  • Cazorla Almeida, Francisco Javier  (autor)
  • Valero Cortes, Mateo  (autor)