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MAPC: memory access pattern based controller

Autor
Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
24th International Conference on Field Programmable Logic and Applications
Any de l'edició
2014
Data de presentació
2014-09
Llibre d'actes
Conference Digest: 24th International Conference on Field Programmable Logic and Applications: Technische Universität München, Germany: September 1-5, 2014
Pàgina inicial
1
Pàgina final
4
Editor
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/FPL.2014.6927397 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/27368 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6927397 Obrir en finestra nova
Resum
Traditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling the accesses at the memory system level and exploring data accesses on the memory systems. In this paper, we propose a memory access pattern based controller (MAPC). MAPC organizes data accesses in descriptors, prioritizes them with respect to the number and size of transfer req...
Citació
Hussain, T. [et al.]. MAPC: memory access pattern based controller. A: International Conference on Field Programmable Logic and Applications. "Conference Digest: 24th International Conference on Field Programmable Logic and Applications: Technische Universität München, Germany: September 1-5, 2014". Munich: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 1-4.
Paraules clau
Dynamic Power, Hardware Resources, Memory Access Patterns, Memory Systems, Multi-core Systems, Number And Size, Processing Core, System Designers
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants