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Dynamic-vector execution on a general purpose EDGE chip multiprocessor

Autor
Duric, M.; Palomar, O.; Smith, A.; Stanic, M.; Unsal, O.; Cristal, A.; Valero, M.; Burger, D.; Veidenbaum, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
XIV International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
Any de l'edició
2014
Data de presentació
2014-07
Llibre d'actes
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XIV): proceedings: July 14-17, 2014: Samos, Greece
Pàgina inicial
18
Pàgina final
25
Editor
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/SAMOS.2014.6893190 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/27788 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6893190 Obrir en finestra nova
Resum
This paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector architecture as an accelerator, our technique leverages the resources of each CMP core to mimic the functionality of a vector processor. The morphing provides dynamic vector execution (DVX) on a general purpose CMP, by adding minimal hardware for vector control. DVX enhances the ve...
Citació
Duric, M. [et al.]. Dynamic-vector execution on a general purpose EDGE chip multiprocessor. A: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. "International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XIV): proceedings: July 14-17, 2014: Samos, Greece". Samos: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 18-25.
Paraules clau
Dlp Accelerator, Dvx Enabled 4-core Edge Cmp, Edge Architecture, Cost-effective Technique, Data Parallel Workloads, Dedicated Accelerator, Dynamic Vector Execution, Energy Efficient Substrate, Energy-delay Product, Explicit Data Graph Execution, Functionality, General Purpose Cmp, General Purpose Edge Chip, Multiprocessor, High Performance Vector Design, Low Power Chip Multiprocessor, Minimal Hardware, Modest Processor, Special-purpose Vector Architecture, Vector Accelerator, Vector Control, Vector Processor, Microprocessor Chips, Multiprocessing Systems, Computational Modeling, Computer Architecture, Hardware, Instruction Sets, Message Systems, Registers, Vectors
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Duric, Milovan  (autor ponent)
  • Palomar Perez, Oscar  (autor ponent)
  • Smith, Aaron  (autor ponent)
  • Stanic, Milan  (autor ponent)
  • Unsal, Osman Sabri  (autor ponent)
  • Cristal Kestelman, Adrian  (autor ponent)
  • Valero Cortes, Mateo  (autor ponent)
  • Burger, Doug  (autor ponent)
  • Veidenbaum, Alex  (autor ponent)