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Dynamic-vector execution on a general purpose EDGE chip multiprocessor

Autor
Duric, M.; Palomar, O.; Smith, A.; Stanic, M.; Unsal, O.; Cristal, A.; Valero, M.; Burger, D.; Veidenbaum, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
XIV International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
Any de l'edició
2014
Data de presentació
2014-07
Llibre d'actes
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XIV): proceedings: July 14-17, 2014: Samos, Greece
Pàgina inicial
18
Pàgina final
25
Editor
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/SAMOS.2014.6893190 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/27788 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6893190 Obrir en finestra nova
Resum
This paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector architecture as an accelerator, our technique leverages the resources of each CMP core to mimic the functionality of a vector processor. The morphing provides dynamic vector execution (DVX) on a general purpose CMP, by adding minimal hardware for vector control. DVX enhances the ve...
Citació
Duric, M. [et al.]. Dynamic-vector execution on a general purpose EDGE chip multiprocessor. A: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. "International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XIV): proceedings: July 14-17, 2014: Samos, Greece". Samos: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 18-25.
Paraules clau
Computational modeling, Computer architecture, Cost-effective technique, DLP accelerator, DVX enabled 4-core EDGE CMP, Data parallel workloads, Dedicated accelerator, Dynamic vector execution, EDGE architecture, Energy efficient substrate, Energy-delay product, Explicit data graph execution, Functionality, General purpose CMP, General purpose EDGE chip, Hardware, High performance vector design, Instruction sets, Low power chip multiprocessor, Message systems, Microprocessor chips, Minimal hardware, Modest processor, Multiprocessing systems, Multiprocessor, Registers, Special-purpose vector architecture, Vector accelerator, Vector control, Vector processor, Vectors
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Duric, Milovan  (autor ponent)
  • Palomar Perez, Oscar  (autor ponent)
  • Smith, Aaron  (autor ponent)
  • Stanic, Milan  (autor ponent)
  • Unsal, Osman Sabri  (autor ponent)
  • Cristal Kestelman, Adrian  (autor ponent)
  • Valero Cortes, Mateo  (autor ponent)
  • Burger, Doug  (autor ponent)
  • Veidenbaum, Alex  (autor ponent)