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Feasibility of Embedded DRAM Cells on FinFET Technology

Autor
Amat, Esteve; Calomarde, A.; Moll, F.; Canal, R.; Rubio, A.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on computers
Data de publicació
2016-04-01
Volum
65
Número
4
Pàgina inicial
1068
Pàgina final
1074
DOI
https://doi.org/10.1109/TC.2014.2375204 Obrir en finestra nova
Projecte finançador
Aproximación multinivel al diseño orientado a la fiabilidad de circuitos integrados analógicos y digitales
Terascale Reliable Adaptive Memory System
URL
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6977916 Obrir en finestra nova
Resum
In this paper, we analyze the suitability of implementing embedded DRAM (eDRAM) cells on FinFET technology compared to classical planar MOSFETs. The results show a significant improvement in overall cell performance for multi-gate devices. While pFinFET-based memories showed better cell behavior and variability robustness, mixed n/p FinFET cells had the highest working frequency and a negligible impact on degradation. Finally, we show that a multiple fin-height strategy can be used to reduce the...
Paraules clau
CMOS, DEVICES, FinFET, LOGIC, SRAM, eDRAM and temperature
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
VIRTUOS - Virtualisation and Operating Systems

Participants