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PMSS: a programmable memory system and scheduler for complex memory patterns

Autor
Hussain, T.; Haider, A.; Ayguade, E.
Tipus d'activitat
Article en revista
Revista
Journal of parallel and distributed computing
Data de publicació
2014-10
Volum
74
Número
15
Pàgina inicial
2983
Pàgina final
2993
DOI
https://doi.org/10.1016/j.jpdc.2014.06.005 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/27820 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S0743731514001075 Obrir en finestra nova
Resum
HPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. However, applications are getting more complex, with multiple kernels and complex data arrangements, generating overhead while scheduling/managing system resources. Due to this reason all classes of multi threaded machines–minicomputer to supercomputer–require to have effi...
Citació
Hussain, T.; Haider, A.; Ayguade, E. PMSS: a programmable memory system and scheduler for complex memory patterns. "Journal of parallel and distributed computing", Octubre 2014, vol. 74, núm. 15, p. 2983-2993.
Paraules clau
DRAM, FPGA, HPC, Xilkernel
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants