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AMC: Advanced Multi-accelerator Controller

Autor
Hussain, T.; Haider, A.; Gursal, S.; Ayguade, E.
Tipus d'activitat
Article en revista
Revista
Parallel computing
Data de publicació
2015-01
Volum
41
Pàgina inicial
14
Pàgina final
30
DOI
https://doi.org/10.1016/j.parco.2014.10.003 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/78376 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S0167819114001264 Obrir en finestra nova
Resum
The rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS multi-accelerator system requires a microprocessor (master core) that manages memory and schedules accelerators. In a real environment, such HLS multi-accelerator systems do not give a perfect performance due to memory bandwidth issues. Thus, a system demands a memory manager a...
Citació
Hussain, T., Haider, A., Gursal, S., Ayguade, E. AMC: Advanced Multi-accelerator Controller. "Parallel computing", Gener 2015, vol. 41, p. 14-30.
Paraules clau
FPGA, HLS, HPC, Master core
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Hussain, Tassadaq  (autor)
  • Haider, Amna  (autor)
  • Gursal, Shakaib A.  (autor)
  • Ayguade Parra, Eduard  (autor)

Arxius