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Reducing memory traffic via redundant store instructions

Autor
Molina, C.; Gonzalez, A.; Tubella, J.
Tipus d'activitat
Article en revista
Revista
Lecture notes in computer science
Data de publicació
1999-03
Volum
1593
Pàgina inicial
1246
Pàgina final
1249
DOI
https://doi.org/10.1007/BFb0100700 Obrir en finestra nova
URL
http://link.springer.com/chapter/10.1007%2FBFb0100700 Obrir en finestra nova
Resum
Some memory writes have the particular behaviour of not modifying memory since the value they write is equal to the value before the write. These kind of stores are what we call Redundant Stores. In this paper we study the behaviour of these particular stores and show that a significant saving on memory traffic between the first and second level caches can be avoided by exploiting this feature. We show that with no additional hardware (just a simple comparator) and without increasing the cache l...
Paraules clau
Cache storage, Memory architecture
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants