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Hardware support for early register release

Autor
Monreal, T.; Viñals, V.; Gonzalez, A.; Valero, M.
Tipus d'activitat
Article en revista
Revista
International journal of high performance computing and networking
Data de publicació
2005
Volum
3
Número
2/3
Pàgina inicial
83
Pàgina final
94
DOI
https://doi.org/10.1504/IJHPCN.2005.008029 Obrir en finestra nova
URL
http://www.inderscienceonline.com/doi/abs/10.1504/IJHPCN.2005.008029 Obrir en finestra nova
Resum
Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is closely related to the size and number of ports of the register file. In conventional register-renaming schemes, register releasing is conservatively done only after the instruction that redefines the same register is committed. Instead, we propose a scheme that releases registers as soon as the pr...
Paraules clau
Optimisation, Out-of-order processors, Precise exceptions, Register files, Register releasing, Register renaming
Grup de recerca
ARCO - Microarquitectura i Compiladors
CAP - Grup de Computació d'Altes Prestacions

Participants