Xiang, D.; Casas-Turu, J.; Massó-Muratel, S.; Wang, T. IEEE Transactions on Sustainable Energy Vol. 8, num. 1, p. 395-403 DOI: 10.1109/TSTE.2016.2601645 Data de publicació: 2017-01-01 Article en revista
Low-voltage ride-through (LVRT) capability is now required for all large-scale wind turbines (WTs) connected to the grid. This paper presents an on-site LVRT testing method for full-power converter (FPC) WTs. The new method makes use of the already installed WTs to emulate the grid and produce a given fault for the WT under test. To guarantee the safety of grid, both the test and grid emulation WTs are disconnected from the network and operate in stand-alone mode during the test. The system configuration, testing procedure, and control strategies are studied in the paper. Practical issues including the capability of emulated grid, WT overspeed limitation, network impedance, and fault conditions emulation are discussed. A wind farm with typical 2-MW FPC permanent magnet synchronous generator (PMSG) WTs is modeled in MATLAB. Simulation results show that with only proper modifications of a WT control algorithm, it is feasible to conduct on-site a series of LVRT tests for the FPC WT safely under given conditions.
This paper compares and discusses four
techniques for model order reduction based on compressed
sensing (CS), less relevant basis removal (LRBR), principal
component analysis (PCA) and partial least squares (PLS). CS
and PCA have already been used for reducing the order of power
amplifier (PA) behavioral models for digital predistortion (DPD)
purposes. While PLS, despite being popular in some signal
processing areas, to the best author’s knowledge, still has not
been used in the PA linearization field. Finally, the LRBR is an
iterative search algorithm proposed by the authors in this paper
for the sake of comparison. Experimental results are presented
and the advantages and drawbacks of each method discussed.
Fourth-generation (4G) communication systems based on orthogonal frequency division multiplexing (OFDM) and the proposed backwards compatible fifth-generation (5G) variants, like filter-bank multicarrier (FBMC), are based on modulation techniques that allow significantly increased spectral efficiency and capacity in mobile radio access networks (RANs). However, the use of these modulation techniques impacts the requirements of the radio base stations, which have been traditionally the most energy-consuming element of mobile networks, accounting for up to 80% of the energy consumption of RANs . Non-constant envelope-modulation techniques with high peak-to-average power ratios (PAPRs) require highly linear power amplifier (PA) amplitude and phase responses to fulfill stringent spectral mask and modulation accuracy requirements. This is often achieved with significant PA back-off, which considerably reduces PA efficiency because the PA's maximum efficiency is achieved near the saturation point.
This paper presents a study oriented at reducing the
computational complexity of least squares (LS) identification of
the parameters describing power amplifier’s (PA) behavioral
models. To reduce the dimensions of the input data matrix, two
strategies are proposed: i) model order reduction based on the
principal component analysis (PCA) theory; and ii) apply a meshselecting
method to reduce the number of required equations. In
this context, the effect of using under-sampling ADCs for the LS
parameter extraction aiming at reducing the costs of PA
identification is also discussed. Finally, the trade-off between the
cost/complexity reduction and quality (or identification accuracy)
loss is evaluated. The proposed strategies can also be considered
for low-computational cost digital predistortion implementations.
Montoro, G.; Wang, T.; López, D.; Ruiz, M.; García, J. A.; Gilabert, Pere L. Simposium Nacional de la Unión Científica Internacional de Radio p. 1-4 Data de presentació: 2015-09-03 Presentació treball a congrés
With the increasing demands for higher data rate,
wider signal bandwidth is required, and this imposes high
sampling rate converters in the communications equipment.
This paper provides and analyzes experimental results obtained
from testing some of the most promising techniques able to
reduce the sampling rate speed of the Analog to Digital
Converters and Digital to Analog Converters to be used in the
implementation of Digital Predistorters. In a first section, an
overview of several of the recently published sampling rate
reduction techniques is done, and later it’s included a section
where the author’s activities related to the digital predistortion
of wideband signals are explained, and some of their last
research activities and results in sampling rate and bandwidth
reduction are provided.