Carregant...
Carregant...

Vés al contingut (premeu Retorn)

Instruction scheduling for a clustered VLIW processor with a word-interleaved cache

Autor
Gibert, E.; Sánchez, J.; Gonzalez, A.
Tipus d'activitat
Article en revista
Revista
Concurrency and Computation: Practice and Experience
Data de publicació
2006-09
Volum
18
Número
11
Pàgina inicial
1391
Pàgina final
1411
DOI
https://doi.org/10.1002/cpe.1013 Obrir en finestra nova
URL
http://onlinelibrary.wiley.com/doi/10.1002/cpe.1013/full Obrir en finestra nova
Resum
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully distributed architectures, where the register file, the functional units and the data cache are partitioned, are particularly effective to deal with these constraints and moreover they are very scalable. In this paper, effective instruction scheduling techniques for a word-interleaved cache clustered VLIW processor are presented. Such scheduling techniques rely on (i) loop unrolling...
Paraules clau
Cache storage, Instruction sets, Multiprocessing systems, Parallel architectures, Processor scheduling
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants