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Analysis of dissipation energy of switching digital CMOS gates with coupled outputs

Autor
Moll, F.; Roca, M.; Isern, E.
Tipus d'activitat
Article en revista
Revista
Microelectronics journal
Data de publicació
2003-09
Volum
34
Número
9
Pàgina inicial
833
Pàgina final
842
DOI
https://doi.org/10.1016/S0026-2692(03)00133-2 Obrir en finestra nova
URL
http://www.sciencedirect.com/science/article/pii/S0026269203001332 Obrir en finestra nova
Resum
The current trend of a high level of integration causes an important parasitic coupling between lines, that is, a capacitance between lines exists in addition to capacitance to ground. This paper calculates how this coupling capacitance influences the power consumption, taking into account the value of the capacitance, the switching activity of the coupled lines, and the influence of relative delay between transitions in the coupled lines.
Paraules clau
Crosstalk-noise, Interconnections, Low-power-design, Power-consumption-model, Switching-activity
Grup de recerca
HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions

Participants