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RTL synthesis: From logic synthesis to automatic pipelining

Autor
Cortadella, J.; Galceran, M.; Kishinevsky, M.; Sapatnekar, S.
Tipus d'activitat
Article en revista
Revista
Proceedings of the IEEE
Data de publicació
2015-11-01
Volum
103
Número
11
Pàgina inicial
2061
Pàgina final
2075
DOI
https://doi.org/10.1109/JPROC.2015.2456189 Obrir en finestra nova
Projecte finançador
Modelos y métodos computacionales para datos masivos estructurados
Repositori
http://hdl.handle.net/2117/82027 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7275092 Obrir en finestra nova
Resum
Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the advent of techniques for automatic pipelining based on elastic timing, either synchronous or asynchronous. The emergence of these techniques can enable a productive interaction with tools that can do microarchitectural exploration of complex designs.
Citació
Cortadella, J., Galceran, M., Kishinevsky, M., Sapatnekar, S. RTL synthesis: From logic synthesis to automatic pipelining. "Proceedings of the IEEE", 01 Novembre 2015, vol. 103, núm. 11, p. 2061-2075.
Paraules clau
Architectural pipelining, Design automation, High-level synthesis, Logic synthesis, Timing elasticity
Grup de recerca
ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals

Participants

  • Cortadella Fortuny, Jordi  (autor)
  • Galceran Oms, Marc  (autor)
  • Kishinevsky, Mike  (autor)
  • Sapatnekar, Sachin S.  (autor)

Arxius