This article describes a low-noise readout amplifier for a post-CMOS BEOL (Back End Of Line) surface micromachining capacitive accelerometer. Simulations show 300.0µG/rt-Hz acceleration and 4.2 zF/rt-Hz capacitance noise floors while chopping at 1MHz and having a power consumption of 1.38mW. The performed noise minimization is described, comprising input transistor pair type election, optimum input pair inversion region and dimensions using an all-region EKV model and equations describing paras...
This article describes a low-noise readout amplifier for a post-CMOS BEOL (Back End Of Line) surface micromachining capacitive accelerometer. Simulations show 300.0µG/rt-Hz acceleration and 4.2 zF/rt-Hz capacitance noise floors while chopping at 1MHz and having a power consumption of 1.38mW. The performed noise minimization is described, comprising input transistor pair type election, optimum input pair inversion region and dimensions using an all-region EKV model and equations describing parasitics and loop characteristics of the circuit. Simulations have been included that verify the theoretical model accuracy and demonstrate final circuit noise performance. The circuit layout has been taped out and testchip availability is expected soon for experimental measurements.
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