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Test escapes of stuck-open faults caused by parasitic capacitances and leakage currents

Autor
Arumi, D.; Rodriguez-Montanes, R.; Figueras, J.
Tipus d'activitat
Article en revista
Revista
IEEE transactions on very large scale integration (VLSI) systems
Data de publicació
2015-09-24
Volum
24
Número
5
Pàgina inicial
1739
Pàgina final
1748
DOI
https://doi.org/10.1109/TVLSI.2015.2477103 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/86699 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7275171 Obrir en finestra nova
Resum
Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technolo...
Citació
Arumi, D., Rodriguez, R., Figueras, J. Test escapes of stuck-open faults caused by parasitic capacitances and leakage currents. "IEEE transactions on very large scale integration (VLSI) systems", 24 Setembre 2015, vol. 24, núm. 5, p. 1739-1748.
Paraules clau
Integrated circuit (IC) testing, leakage currents, parasitic capacitances, stuck-open faults (SOFs), test escapes
Grup de recerca
QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat

Participants

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