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  • Energy Characterization Methodologies for CMP/SMT Processor Systems

     Bertran Monfort, Ramon
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Software-managed power reduction in Infiniband links  Open access

     Dickov, Branimir; Pericas, Miquel; Carpenter, Paul M.; Navarro, Nacho; Ayguade Parra, Eduard
    International Conference on Parallel Processing
    p. 311-320
    DOI: 10.1109/ICPP.2014.40
    Presentation's date: 2014-09
    Presentation of work at congresses
    Access to the full text
  • Enabling preemptive multiprogramming on GPUs  Open access

     Tanasic, Ivan; Gelado Fernandez, Isaac; Cabezas, Javier; Ramirez Bellido, Alejandro; Navarro, Nacho; Valero Cortes, Mateo
    International Symposium on Computer Architecture
    p. 193-204
    DOI: 10.1109/ISCA.2014.6853208
    Presentation's date: 2014-06-14
    Presentation of work at congresses
    Access to the full text
  • Experimental assessment of a high performance back-end PCE for Flexgrid optical network re-optimization

     Gifre Renom, Lluis; Velasco Esteban, Luis; Navarro, Nacho; Junyent Giralt, Gabriel
    Optical Fiber Communications Conference and Exposition and National Fiber Optic Engineers Conference
    p. 1-3
    DOI: 10.1364/OFC.2014.W4A.3
    Presentation's date: 2014-03
    Presentation of work at congresses
  • Models de Programacio i Entorns d'eXecució PARal.lels

     Becerra Fontal, Yolanda; Carrera Perez, David; Corbalan Gonzalez, Julita; Cortes Rossello, Antonio; Costa Prats, Juan Jose; Farreras Esclusa, Montserrat; Gil Gómez, Maria Luisa; Gonzalez Tallada, Marc; Guitart Fernández, Jordi; Herrero Zaragoza, José Ramón; Labarta Mancho, Jesus Jose; Martorell Bofill, Xavier; Navarro, Nacho; Nin Guerrero, Jordi; Torres Viñals, Jordi; Tous Liesa, Ruben; Utrera Iglesias, Gladys Miriam; Ayguade Parra, Eduard
    Competitive project
  • The TERAFLUX Project: Exploiting the dataflow paradigm in next generation teradevices

     Solinas, Marco; Badia Sala, Rosa Maria; Bodin, François; Cohen, Albert; Evripidou, Paraskevas; Faraboschi, Paolo; Fechner, Bernhard; Gao, Guang R.; Garbade, Arne; Girbal, Sylvain; Goodman, Daniel; Khan, Behran; Koliai, Souad; Li, Feng; Lujan, Mikel; Morin, Laurent; Mendelson, Avi; Navarro, Nacho; Pop, Antoniu; Trancoso, Pedro; Ungerer, Theo; Valero Cortes, Mateo; Weis, Sebastian; Watson, Ian; Zuckermann, Stéphane; Giorgi, Roberto
    Euromicro Symposium on Digital Systems Design
    p. 272-279
    DOI: 10.1109/DSD.2013.39
    Presentation's date: 2013-09
    Presentation of work at congresses
  • A systematic methodology to generate decomposable and responsive power models for CMPs

     Bertran Monfort, Ramon; Gonzalez Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguade Parra, Eduard
    IEEE transactions on computers
    Vol. 62, num. 7, p. 1289-1302
    DOI: 10.1109/TC.2012.97
    Date of publication: 2013-07
    Journal article
  • Architecture of a specialized back-end high performance computing-based PCE for flexgrid networks

     Gifre Renom, Lluis; Velasco Esteban, Luis; Navarro, Nacho
    International Conference on Transparent Optical Networks
    p. Mo.C4.3-1-Mo.C4.3-4
    DOI: 10.1109/ICTON.2013.6602716
    Presentation's date: 2013-06
    Presentation of work at congresses
  • Comparison based sorting for systems with multiple GPUs

     Tanasic, Ivan; Vilanova, Lluís; Jorda, Marc; Cabezas, Javier; Gelado Fernandez, Isaac; Navarro, Nacho; Hwu, Wen-mei W.
    Workshop on General Purpose Processing Using GPUs
    p. 1-11
    DOI: 10.1145/2458523.2458524
    Presentation's date: 2013-03
    Presentation of work at congresses
  • A template system for the efficient compilation of domain abstractions onto reconfigurable computers

     Shafiq, Muhammad; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    Journal of systems architecture
    Vol. 59, num. 2, p. 91-102
    DOI: 10.1016/j.sysarc.2012.10.002
    Date of publication: 2013-02
    Journal article
  • Design space explorations for streaming accelerators using streaming architectural simulator  Open access

     Shafiq, Muhammad; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    International Bhurban Conference on Applied Sciences and Technology
    p. 169-178
    DOI: 10.1109/IBCAST.2013.6512151
    Presentation's date: 2013-01
    Presentation of work at congresses
    Access to the full text
  • Hardware-software coherence protocol for the coexistence of caches and local memories

     Alvarez, Lluc; Vilanova, Lluis; Gonzalez Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguade Parra, Eduard
    International Conference for High Performance Computing, Networking, Storage and Analysis
    p. Article No. 89-
    DOI: 10.1109/TC.2013.194
    Presentation's date: 2012-11-07
    Presentation of work at congresses
  • Counter-based power modeling methods: top-down vs. bottom-up

     Bertran Monfort, Ramon; Gonzalez Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguade Parra, Eduard
    The computer journal (Kalispell, Mont.)
    Vol. 56, num. 2, p. 198-213
    DOI: 10.1093/comjnl/bxs116
    Date of publication: 2012-08-24
    Journal article
  • PPMC: hardware scheduling and memory management support for multi accelerators

     Hussain, Tassadaq; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    International Conference on Field Programmable Logic and Applications
    p. 571-574
    DOI: 10.1109/FPL.2012.6339373
    Presentation's date: 2012-08
    Presentation of work at congresses
  • POTRA: a framework for building power models for next generation multicore architectures

     Bertran Monfort, Ramon; Gonzalez Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguade Parra, Eduard
    ACM SIGMETRICS performance evaluation review
    Vol. 40, num. 1, p. 427-428
    DOI: 10.1145/2318857.2254827
    Date of publication: 2012-06
    Journal article
  • Assessing the impact of network compression on molecular dynamics and finite element methods

     Dickov, Branimir; Pericas, Miquel; Houzeaux, Guillaume; Navarro, Nacho; Ayguade Parra, Eduard
    IEEE International Conference on High Performance Computing and Communications
    p. 588-597
    DOI: 10.1109/HPCC.2012.85
    Presentation's date: 2012-06
    Presentation of work at congresses
  • Architectural explorations for streaming accelerators with customized memory layouts  Open access

     Shafiq, Muhammad
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • BSArc: blacksmith streaming architecture for HPC accelerators

     Shafiq, Muhammad; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    ACM International Conference on Computing Frontiers
    p. 23-32
    DOI: 10.1145/2212908.2212914
    Presentation's date: 2012-05
    Presentation of work at congresses
  • PPMC: a programmable pattern based memory controller

     Hussain, Tassadaq; Shafiq, Muhammad; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    International IEEE/ACM Symposium on Applied Reconfigurable Computing
    p. 89-101
    DOI: 0.1007/978-3-642-28365-9_8
    Presentation's date: 2012-03
    Presentation of work at congresses
  • Energy accounting for shared virtualized environments under DVFS using PMC-based power models

     Bertran Monfort, Ramon; Becerra Fontal, Yolanda; Carrera Perez, David; Beltran Querol, Vicenç; Gonzalez Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Torres Viñals, Jordi; Ayguade Parra, Eduard
    Future generation computer systems
    Vol. 28, num. 2, p. 457-468
    DOI: 10.1016/j.future.2011.03.007
    Date of publication: 2012-02
    Journal article
  • HIPEAC 3 - European Network of Excellence on HighPerformance Embedded Architecture and Compilers

     Gil Gómez, Maria Luisa; Navarro, Nacho; Martorell Bofill, Xavier; Valero Cortes, Mateo; Ayguade Parra, Eduard; Ramirez Bellido, Alejandro; Badia Sala, Rosa Maria; Labarta Mancho, Jesus Jose; Llaberia Griño, Jose M.
    Competitive project
  • Hardware and software support for distributed shared memory in chip multiprocessors

     Villavieja Prados, Carlos
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • The data transfer engine: towards a software controlled memory hierarchy

     Garcia Flores, Victor; Rico Carro, Alejandro; Villavieja Prados, Carlos; Navarro, Nacho; Ramirez Bellido, Alejandro
    International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
    p. 215-218
    Presentation's date: 2012
    Presentation of work at congresses
  • POTRA: a framework for building power models for next generation multicore architectures

     Bertran Monfort, Ramon; Gonzalez Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguade Parra, Eduard
    ACM SIGMETRICS/PERFORMANCE joint International Conference on Measurement and Modeling of Computer Systems
    p. 427-428
    DOI: 10.1145/2254756.2254827
    Presentation's date: 2012
    Presentation of work at congresses
  • Implementation of a reverse time migration kernel using the HCE high level synthesis tool

     Hussain, Tassadaq; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    International Conference on Field-Programmable Technology
    p. 1-8
    DOI: 10.1109/FPT.2011.6132717
    Presentation's date: 2011-12-12
    Presentation of work at congresses
  • DiDi: mitigating the performance impact of TLB shootdowns using a shared TLB directory

     Villavieja Prados, Carlos; Karakostas, Vasileios; Vilanova, Lluis; Etsion, Yoav; Ramirez Bellido, Alejandro; Mendelson, Avi; Navarro, Nacho; Cristal Kestelman, Adrián; Unsal, Osman Sabri
    International Conference on Parallel Architectures and Compilation Techniques
    p. 340-349
    DOI: 10.1109/PACT.2011.65
    Presentation's date: 2011-10-04
    Presentation of work at congresses
  • FELI: HW/SW support for on-chip distributed shared memory in multicores

     Villavieja Prados, Carlos; Etsion, Yoav; Ramirez Bellido, Alejandro; Navarro, Nacho
    International European Conference on Parallel and Distributed Computing
    p. 282-294
    DOI: 10.1007/978-3-642-23400-2_27
    Presentation's date: 2011-09-02
    Presentation of work at congresses
  • Design space exploration for aggressive core replication schemes in CMPs

     Álvarez Martí, Lluc; Bertran Monfort, Ramon; Gonzalez Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguade Parra, Eduard
    International Symposium on High Performance Distributed Computing
    p. 269-270
    DOI: 10.1145/1996130.1996169
    Presentation's date: 2011-06-08
    Presentation of work at congresses
  • TARCAD: a template architecture for reconfigurable accelerator designs

     Shafiq, Muhammad; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    IEEE Symposium on Application Specific Processors
    p. 8-15
    DOI: 10.1109/SASP.2011.5941071
    Presentation's date: 2011-06-05
    Presentation of work at congresses
  • Assessing accelerator-based HPC reverse time migration

     Araya Polo, Mauricio; Cabezas, Javier; Hanzich, Mauricio; Pericas, Miquel; Rubio, Fèlix; Gelado Fernandez, Isaac; Shafiq, Muhammad; Morancho Llena, Enrique; Navarro, Nacho; Ayguade Parra, Eduard; Cela Espin, Jose M.; Valero Cortes, Mateo
    IEEE transactions on parallel and distributed systems
    Vol. 22, num. 1, p. 147-162
    DOI: 10.1109/TPDS.2010.144
    Date of publication: 2011-01
    Journal article
  • Multicore: the view from Europe

     Valero Cortes, Mateo; Navarro, Nacho
    IEEE micro
    Vol. 30, num. 5, p. 2-4
    DOI: 10.1109/MM.2010.93
    Date of publication: 2010-11-18
    Journal article
  • FEM: a step towards a common memory layout for FPGA based accelerators

     Shafiq, Muhammad; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    International Conference on Field Programmable Logic and Applications
    p. 568-573
    DOI: 10.1109/FPL.2010.111
    Presentation's date: 2010-08
    Presentation of work at congresses
  • On the programmability of heterogeneous massively-parallel computing systems  Open access

     Gelado Fernandez, Isaac
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Streaming scatter/gather DMA controller for hardware accelerators

     Hussain, Tassadaq; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
    Presentation's date: 2010-07
    Presentation of work at congresses
  • Decomposable and responsive power models for multicore processors using performance counters

     Bertran Monfort, Ramon; Gonzalez Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguade Parra, Eduard
    International Conference for High Performance Computing, Networking, Storage and Analysis
    p. 147-158
    DOI: 10.1145/1810085.1810108
    Presentation's date: 2010-06-04
    Presentation of work at congresses
  • Local memory design space exploration for high-performance computing

     Bertran Monfort, Ramon; Gonzalez Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguade Parra, Eduard
    The Computer journal (paper)
    Vol. 54, num. 5, p. 786-799
    DOI: 10.1093/comjnl/bxq026
    Date of publication: 2010-03-23
    Journal article
  • An asymmetric distributed shared memory model for heterogeneous parallel systems  Open access

     Gelado Fernandez, Isaac; E. Stone, John; Cabezas, Javier; Patel, Sanjay; Navarro, Nacho; W. Hwu, Wen-mei
    International Conference on Architectural Support for Programming Languages and Operating Systems
    p. 347-358
    DOI: 10.1145/1736020.1736059
    Presentation's date: 2010-03-13
    Presentation of work at congresses
    Access to the full text
  • An asymmetric distributed shared memory model for heterogeneous parallel systems

     Gelado Fernandez, Isaac; Stone, John E.; Cabezas, Javier; Patel, Sanjay; Navarro, Nacho; HEI HWU, WEN
    Computer architecture news
    Vol. 38, num. 1, p. 347-358
    DOI: 10.1145/1735970.1736059
    Date of publication: 2010
    Journal article
  • Exploiting Dataflow Parallelism in Teradevice Computing (TERAFLUX)

     Badia Sala, Rosa Maria; Ramirez Bellido, Alejandro; Navarro, Nacho; Gil Gómez, Maria Luisa
    Competitive project
  • DISEÑO DE REDES INALÁMBRICAS INTEROPERABLES CON CAPACIDAD PARA SENSORES HETEROGÉNEOS

     Jimenez Castells, Marta; Gil Gómez, Maria Luisa; Navarro, Nacho
    Competitive project
  • Row-interleaved streaming data flow implementation of sparse matrix vector multiplication in FPGA

     Dickov, Branimir; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    HiPEAC Workshop on Reconfigurable Computing
    p. 1-10
    Presentation's date: 2010-01
    Presentation of work at congresses
  • Exploiting memory customization in FPGA for 3D stencil computations

     Shafiq, Muhammad; Pericas, Miquel; De la Cruz Martinez, Raul; Araya Polo, Mauricio; Navarro, Nacho; Ayguade Parra, Eduard
    International Conference on Field-Programmable Technology
    p. 38-45
    DOI: 10.1109/FPT.2009.5377644
    Presentation's date: 2009-12
    Presentation of work at congresses
  • High-performance reverse time migration on GPU  Open access

     Cabezas, Javier; Ayala Polo, Mauricio; Gelado Fernandez, Isaac; Morancho Llena, Enrique; Navarro, Nacho; Cela Espin, Jose M.
    International Conference of the Chilean Computer Science Society
    p. 77-86
    DOI: 10.1109/SCCC.2009.19
    Presentation's date: 2009-11
    Presentation of work at congresses
    Access to the full text
  • MPEXPAR: MODELS DE PROGRAMACIO I ENTORNS D'EXECUCIO PARAL·LELS

     Nou Castell, Ramon; Gonzalez Tallada, Marc; Gil Gómez, Maria Luisa; Navarro, Nacho; Sirvent Pardell, Raül; Guitart Fernández, Jordi; Carrera Perez, David; Martorell Bofill, Xavier; Herrero Zaragoza, José Ramón; Torres Viñals, Jordi; Badia Sala, Rosa Maria; Becerra Fontal, Yolanda; Cortes Rossello, Antonio; Corbalan Gonzalez, Julita; Costa Prats, Juan Jose; Farreras Esclusa, Montserrat; Alonso López, Javier; Tejedor Saavedra, Enric; Labarta Mancho, Jesus Jose; Ayguade Parra, Eduard
    Competitive project
  • Mapping sparse matrix-vector multiplication (SMVM) on FPGA - reconfigurable supercomputing

     Dickov, Branimir; Pericas, Miquel; Ayguade Parra, Eduard; Navarro, Nacho
    International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
    Presentation's date: 2009-07
    Presentation of work at congresses
  • A streaming based high performance FPGA core for 3D reverse time migration

     Shafiq, Muhammad; Pericas, Miquel; Navarro, Nacho; Ayguade Parra, Eduard
    International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
    Presentation's date: 2009-07
    Presentation of work at congresses
  • CASES 2007 guest editors' introduction

     Lumetta, Steven S.; Navarro, Nacho
    Design automation for embedded systems
    Vol. 13, num. 1-2, p. 89-
    DOI: 10.1007/s10617-008-9037-8
    Date of publication: 2009-06
    Journal article
  • Cetra: A Trace and Analysis Framework for the Evaluation of Cell BE Systems

     Merino, Julio; Alvarez, Lluc; Gil Gómez, Maria Luisa; Navarro, Nacho
    IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2009)
    p. 43-52
    Presentation's date: 2009-04-27
    Presentation of work at congresses
  • Linux kernel compaction through cold code swapping

     Chanet, Dominique; Cabezas, Javier; Morancho Llena, Enrique; Navarro, Nacho; De Bosschere, Koen
    Lecture notes in computer science
    Vol. 5470, p. 173-200
    DOI: 10.1007/978-3-642-00904-4_10
    Date of publication: 2009-04-22
    Journal article
  • Predictive runtime code scheduling for heterogeneous architectures  Open access

     Jiménez, Víctor; Vilanova, Lluis; Gelado Fernandez, Isaac; Gil Gómez, Maria Luisa; Fursin, Gregori; Navarro, Nacho
    International Conference on High Performance and Embedded Architectures and Compilers
    p. 19-33
    Presentation's date: 2009-01-25
    Presentation of work at congresses
    Access to the full text