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1 to 50 of 209 results
 
  • iONE: an environment for experimentally assessing in-operation network planning algorithms

     Gifre, L.; Navarro, Nacho; Asensio, A.; Ruiz, M.; Velasco, L.
    International Conference on Transparent Optical Networks
    p. 1-4
    DOI: 10.1109/ICTON.2015.7193725
    Presentation's date: 2015-07
    Presentation of work at congresses
  • On the programmability of multi-GPU computing systems

    Universitat Politècnica de Catalunya
    Theses
  • Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures  Open access

     Alvarez, Ll.; Vilanova, L.; Moreto, M.; Casas, M.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.; Valero, M.
    International Symposium on Computer Architecture
    p. 720-732
    DOI: 10.1145/2749469.2750411
    Presentation's date: 2015-06-15
    Presentation of work at congresses
    Access to the full text
  • Automatic parallelization of kernels in shared-memory multi-GPU nodes

     Cabezas, J.; Vilanova, L.; Gelado, I.; Jablin, T.; Navarro, Nacho; Hwu, W.
    ACM/IEEE International Conference on Supercomputing
    p. 3-13
    DOI: 10.1145/2751205.2751218
    Presentation's date: 2015-06-08
    Presentation of work at congresses
  • AXIOM

     Valero, M.; Navarro, Nacho; Martorell, X.; Jimenez, D.; Alvarez, C.
    Competitive project
  • Energy Characterization Methodologies for CMP/SMT Processor Systems

    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Software-managed power reduction in Infiniband links  Open access

     Dickov, B.; Pericas, M.; Carpenter, P.; Navarro, Nacho; Ayguade, E.
    International Conference on Parallel Processing
    p. 311-320
    DOI: 10.1109/ICPP.2014.40
    Presentation's date: 2014-09
    Presentation of work at congresses
    Access to the full text
  • Enabling preemptive multiprogramming on GPUs  Open access

     Tanasic, I.; Gelado, I.; Cabezas, J.; Alex Ramirez; Navarro, Nacho; Valero, M.
    International Symposium on Computer Architecture
    p. 193-204
    DOI: 10.1109/ISCA.2014.6853208
    Presentation's date: 2014-06-14
    Presentation of work at congresses
    Access to the full text
  • Experimental assessment of a high performance back-end PCE for Flexgrid optical network re-optimization

     Gifre, L.; Velasco, L.; Navarro, Nacho; Junyent, G.
    Optical Fiber Communications Conference and Exposition and National Fiber Optic Engineers Conference
    p. 1-3
    DOI: 10.1364/OFC.2014.W4A.3
    Presentation's date: 2014-03
    Presentation of work at congresses
  • Models de Programacio i Entorns d'eXecució PARal.lels

     Becerra, Y.; Carrera, D.; Corbalan, J.; Cortes, A.; Costa, J.; Farreras, M.; Gil, Marisa; Gonzalez, M.; Guitart, J.; Herrero, J.; Labarta, J.; Martorell, X.; Navarro, Nacho; Nin, J.; Torres, J.; Tous, R.; Utrera, G.; Ayguade, E.
    Competitive project
  • The TERAFLUX Project: Exploiting the dataflow paradigm in next generation teradevices

     Solinas, M.; Badia, R.M.; Bodin, F.; Cohen, A.; Evripidou, P.; Faraboschi, P.; Fechner, B.; Gao, G.; Garbade, A.; Girbal, S.; Goodman, D.; Khan, B.; Koliai, S.; Li, F.; Lujan, M.; Morin, L.; Mendelson, A.; Navarro, Nacho; Pop, A.; Trancoso, P.; Ungerer, T.; Valero, M.; Weis, S.; Watson, I.; Zuckermann, S.; Giorgi, R.
    Euromicro Symposium on Digital Systems Design
    p. 272-279
    DOI: 10.1109/DSD.2013.39
    Presentation's date: 2013-09
    Presentation of work at congresses
  • A systematic methodology to generate decomposable and responsive power models for CMPs

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    IEEE transactions on computers
    Vol. 62, num. 7, p. 1289-1302
    DOI: 10.1109/TC.2012.97
    Date of publication: 2013-07
    Journal article
  • Architecture of a specialized back-end high performance computing-based PCE for flexgrid networks

     Gifre, L.; Velasco, L.; Navarro, Nacho
    International Conference on Transparent Optical Networks
    p. Mo.C4.3-1-Mo.C4.3-4
    DOI: 10.1109/ICTON.2013.6602716
    Presentation's date: 2013-06
    Presentation of work at congresses
  • Comparison based sorting for systems with multiple GPUs

     Tanasic, I.; Vilanova, L.; Jorda, M.; Cabezas, J.; Gelado, I.; Navarro, Nacho; Hwu, W.
    Workshop on General Purpose Processing Using GPUs
    p. 1-11
    DOI: 10.1145/2458523.2458524
    Presentation's date: 2013-03
    Presentation of work at congresses
  • A template system for the efficient compilation of domain abstractions onto reconfigurable computers

     Shafiq, M.; Pericas, M.; Navarro, Nacho; Ayguade, E.
    Journal of systems architecture
    Vol. 59, num. 2, p. 91-102
    DOI: 10.1016/j.sysarc.2012.10.002
    Date of publication: 2013-02
    Journal article
  • Design space explorations for streaming accelerators using streaming architectural simulator  Open access

     Shafiq, M.; Pericas, M.; Navarro, Nacho; Ayguade, E.
    International Bhurban Conference on Applied Sciences and Technology
    p. 169-178
    DOI: 10.1109/IBCAST.2013.6512151
    Presentation's date: 2013-01
    Presentation of work at congresses
    Access to the full text
  • Hardware-software coherence protocol for the coexistence of caches and local memories

     Alvarez, L.; Vilanova, L.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    International Conference for High Performance Computing, Networking, Storage and Analysis
    p. Article No. 89-
    DOI: 10.1109/TC.2013.194
    Presentation's date: 2012-11-07
    Presentation of work at congresses
  • Counter-based power modeling methods: top-down vs. bottom-up

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    The computer journal (Kalispell, Mont.)
    Vol. 56, num. 2, p. 198-213
    DOI: 10.1093/comjnl/bxs116
    Date of publication: 2012-08-24
    Journal article
  • PPMC: hardware scheduling and memory management support for multi accelerators

     Hussain, T.; Pericas, M.; Navarro, Nacho; Ayguade, E.
    International Conference on Field Programmable Logic and Applications
    p. 571-574
    DOI: 10.1109/FPL.2012.6339373
    Presentation's date: 2012-08
    Presentation of work at congresses
  • POTRA: a framework for building power models for next generation multicore architectures

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    ACM SIGMETRICS performance evaluation review
    Vol. 40, num. 1, p. 427-428
    DOI: 10.1145/2318857.2254827
    Date of publication: 2012-06
    Journal article
  • Assessing the impact of network compression on molecular dynamics and finite element methods

     Dickov, B.; Pericas, M.; Houzeaux, G.; Navarro, Nacho; Ayguade, E.
    IEEE International Conference on High Performance Computing and Communications
    p. 588-597
    DOI: 10.1109/HPCC.2012.85
    Presentation's date: 2012-06
    Presentation of work at congresses
  • Architectural explorations for streaming accelerators with customized memory layouts  Open access

    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • BSArc: blacksmith streaming architecture for HPC accelerators

     Shafiq, M.; Pericas, M.; Navarro, Nacho; Ayguade, E.
    ACM International Conference on Computing Frontiers
    p. 23-32
    DOI: 10.1145/2212908.2212914
    Presentation's date: 2012-05
    Presentation of work at congresses
  • PPMC: a programmable pattern based memory controller

     Hussain, T.; Shafiq, M.; Pericas, M.; Navarro, Nacho; Ayguade, E.
    International IEEE/ACM Symposium on Applied Reconfigurable Computing
    p. 89-101
    DOI: 0.1007/978-3-642-28365-9_8
    Presentation's date: 2012-03
    Presentation of work at congresses
  • HIPEAC 3 - European Network of Excellence on HighPerformance Embedded Architecture and Compilers

     Gil, Marisa; Navarro, Nacho; Martorell, X.; Valero, M.; Ayguade, E.; Alex Ramirez; Badia, R.M.; Labarta, J.; Llaberia, J.
    Competitive project
  • Energy accounting for shared virtualized environments under DVFS using PMC-based power models

     Bertran, R.; Becerra, Y.; Carrera, D.; Beltran, V.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Torres, J.; Ayguade, E.
    Future generation computer systems
    Vol. 28, num. 2, p. 457-468
    DOI: 10.1016/j.future.2011.03.007
    Date of publication: 2012-02
    Journal article
  • Hardware and software support for distributed shared memory in chip multiprocessors

     Villavieja, C.
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • The data transfer engine: towards a software controlled memory hierarchy

     Garcia, V.; Rico, A.; Navarro, Nacho; Villavieja, C.; Alex Ramirez
    International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
    p. 215-218
    Presentation's date: 2012
    Presentation of work at congresses
  • POTRA: a framework for building power models for next generation multicore architectures

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    ACM SIGMETRICS/PERFORMANCE joint International Conference on Measurement and Modeling of Computer Systems
    p. 427-428
    DOI: 10.1145/2254756.2254827
    Presentation's date: 2012
    Presentation of work at congresses
  • Implementation of a reverse time migration kernel using the HCE high level synthesis tool

     Hussain, T.; Pericas, M.; Navarro, Nacho; Ayguade, E.
    International Conference on Field-Programmable Technology
    p. 1-8
    DOI: 10.1109/FPT.2011.6132717
    Presentation's date: 2011-12-12
    Presentation of work at congresses
  • DiDi: mitigating the performance impact of TLB shootdowns using a shared TLB directory

     Villavieja, C.; Karakostas, V.; Vilanova, L.; Etsion, Y.; Alex Ramirez; Mendelson, A.; Navarro, Nacho; Cristal, A.; Unsal, O.
    International Conference on Parallel Architectures and Compilation Techniques
    p. 340-349
    DOI: 10.1109/PACT.2011.65
    Presentation's date: 2011-10-04
    Presentation of work at congresses
  • FELI: HW/SW support for on-chip distributed shared memory in multicores

     Villavieja, C.; Etsion, Y.; Alex Ramirez; Navarro, Nacho
    International European Conference on Parallel and Distributed Computing
    p. 282-294
    DOI: 10.1007/978-3-642-23400-2_27
    Presentation's date: 2011-09-02
    Presentation of work at congresses
  • Design space exploration for aggressive core replication schemes in CMPs

     Álvarez, L.; Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    International Symposium on High Performance Distributed Computing
    p. 269-270
    DOI: 10.1145/1996130.1996169
    Presentation's date: 2011-06-08
    Presentation of work at congresses
  • TARCAD: a template architecture for reconfigurable accelerator designs

     Shafiq, M.; Pericas, M.; Navarro, Nacho; Ayguade, E.
    IEEE Symposium on Application Specific Processors
    p. 8-15
    DOI: 10.1109/SASP.2011.5941071
    Presentation's date: 2011-06-05
    Presentation of work at congresses
  • Assessing accelerator-based HPC reverse time migration

     Araya, M.; Cabezas, J.; Hanzich, M.; Pericas, M.; Rubio, F.; Gelado, I.; Shafiq, M.; Morancho, E.; Navarro, Nacho; Ayguade, E.; Cela, J.; Valero, M.
    IEEE transactions on parallel and distributed systems
    Vol. 22, num. 1, p. 147-162
    DOI: 10.1109/TPDS.2010.144
    Date of publication: 2011-01
    Journal article
  • Multicore: the view from Europe

     Valero, M.; Navarro, Nacho
    IEEE micro
    Vol. 30, num. 5, p. 2-4
    DOI: 10.1109/MM.2010.93
    Date of publication: 2010-11-18
    Journal article
  • FEM: a step towards a common memory layout for FPGA based accelerators

     Shafiq, M.; Pericas, M.; Navarro, Nacho; Ayguade, E.
    International Conference on Field Programmable Logic and Applications
    p. 568-573
    DOI: 10.1109/FPL.2010.111
    Presentation's date: 2010-08
    Presentation of work at congresses
  • On the programmability of heterogeneous massively-parallel computing systems  Open access

     Gelado, I.
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Streaming scatter/gather DMA controller for hardware accelerators

     Hussain, T.; Pericas, M.; Navarro, Nacho; Ayguade, E.
    International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
    Presentation's date: 2010-07
    Presentation of work at congresses
  • Decomposable and responsive power models for multicore processors using performance counters

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    International Conference for High Performance Computing, Networking, Storage and Analysis
    p. 147-158
    DOI: 10.1145/1810085.1810108
    Presentation's date: 2010-06-04
    Presentation of work at congresses
  • Local memory design space exploration for high-performance computing

     Bertran, R.; Gonzalez, M.; Martorell, X.; Navarro, Nacho; Ayguade, E.
    The Computer journal (paper)
    Vol. 54, num. 5, p. 786-799
    DOI: 10.1093/comjnl/bxq026
    Date of publication: 2010-03-23
    Journal article
  • An asymmetric distributed shared memory model for heterogeneous parallel systems  Open access

     Gelado, I.; E. Stone, J.; Cabezas, J.; Patel, S.; Navarro, Nacho; W. Hwu, W.
    International Conference on Architectural Support for Programming Languages and Operating Systems
    p. 347-358
    DOI: 10.1145/1736020.1736059
    Presentation's date: 2010-03-13
    Presentation of work at congresses
    Access to the full text
  • Exploiting Dataflow Parallelism in Teradevice Computing (TERAFLUX)

     Badia, R.M.; Alex Ramirez; Navarro, Nacho; Gil, Marisa
    Competitive project
  • DISEÑO DE REDES INALÁMBRICAS INTEROPERABLES CON CAPACIDAD PARA SENSORES HETEROGÉNEOS

     Jimenez, M.; Gil, Marisa; Navarro, Nacho
    Competitive project
  • Row-interleaved streaming data flow implementation of sparse matrix vector multiplication in FPGA

     Dickov, B.; Pericas, M.; Navarro, Nacho; Ayguade, E.
    HiPEAC Workshop on Reconfigurable Computing
    p. 1-10
    Presentation's date: 2010-01
    Presentation of work at congresses
  • An asymmetric distributed shared memory model for heterogeneous parallel systems

     Gelado, I.; Stone, J.; Cabezas, J.; Patel, S.; Navarro, Nacho; HEI HWU, W.
    Computer architecture news
    Vol. 38, num. 1, p. 347-358
    DOI: 10.1145/1735970.1736059
    Date of publication: 2010
    Journal article
  • Exploiting memory customization in FPGA for 3D stencil computations

     Shafiq, M.; Pericas, M.; De la Cruz, R.; Araya, M.; Navarro, Nacho; Ayguade, E.
    International Conference on Field-Programmable Technology
    p. 38-45
    DOI: 10.1109/FPT.2009.5377644
    Presentation's date: 2009-12
    Presentation of work at congresses
  • High-performance reverse time migration on GPU  Open access

     Cabezas, J.; Ayala-Polo, M.; Gelado, I.; Morancho, E.; Navarro, Nacho; Cela, J.
    International Conference of the Chilean Computer Science Society
    p. 77-86
    DOI: 10.1109/SCCC.2009.19
    Presentation's date: 2009-11
    Presentation of work at congresses
    Access to the full text
  • MPEXPAR: MODELS DE PROGRAMACIO I ENTORNS D'EXECUCIO PARAL·LELS

     Nou, R.; Gonzalez, M.; Gil, Marisa; Navarro, Nacho; Sirvent, R.; Guitart, J.; Carrera, D.; Martorell, X.; Herrero, J.; Torres, J.; Badia, R.M.; Becerra, Y.; Cortes, A.; Corbalan, J.; Costa, J.; Farreras, M.; Alonso, J.; Tejedor, E.; Labarta, J.; Ayguade, E.
    Competitive project