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  • Non-Speculative Enhancements for the Scheduling Logic

     Gran Tejero, Ruben
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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  • ARQUITECTURA DE COMPUTADORS D'ALTRES PRESTACIONS (CAP)

     Jimenez Castells, Marta; Pericas Gleim, Miquel; Navarro Guerrero, Juan Jose; Llaberia Griño, Jose M.; Llosa Espuny, Jose Francisco; Villavieja Prados, Carlos; Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Ramirez Bellido, Alejandro; Morancho Llena, Enrique; Fernandez Jimenez, Agustin; Pajuelo González, Manuel Alejandro; Olive Duran, Angel; Sanchez Carracedo, Fermin; Moreto Planas, Miquel; Verdu Mula, Javier; Abella Ferrer, Jaume; Valero Cortes, Mateo
    Competitive project

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    On reducing misspeculations on a pipelined scheduler  Open access

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    IEEE International Parallel and Distributed Processing Symposium
    p. 1-12
    DOI: 10.1109/IPDPS.2009.5160990
    Presentation's date: 2009-05
    Presentation of work at congresses

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    Pipelining the scheduling logic, which exposes and exploits the instruction level parallelism, degrades processor performance. In a 4-issue processor, our evaluations show that pipelining the scheduling logic over two cycles degrades performance by 10% in SPEC-2000 integer benchmarks. Such a performance degradation is due to sacrificing the ability to execute dependent instructions in consecutive cycles. Speculative selection is a previously proposed technique that boosts the performance of a processor with a pipelined scheduling logic. However, this new speculation source increases the overall number of misspeculated instructions, and this unuseful work wastes energy. In this work we introduce a non-speculative mechanism named Dependence Level Scheduler (DLS)which not only tolerates the scheduling-logic latency but also reduces the number of misspeculated instructions with respect to a scheduler with speculative selection. In DLS, the selection of a group of one-cycle instructions (producer-level) is overlapped with the wake up in advance of its group of dependent instructions. DLS is not speculative because the group of woken in advance instructions will compete for selection only after issuing all producer-level instructions. On average, DLS reduces the number of misspeculated instructions with respect to a speculative scheduler by 17.9%. From the IPC point of view, the speculative scheduler outperforms DLS by 0.3%. Moreover, we propose two non-speculative improvements to DLS.

  • On Reducing Energy-Consumption by Late-Inserting Instructions into the Issue Queue

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    International Symposium on Low Power Electronics and Design
    p. 371-374
    Presentation's date: 2007-08-29
    Presentation of work at congresses

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  • On Improving a Pipelined Scheduling Logic

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    XVIII Jornadas de Paralelismo. CEDI 2007 II Congreso Español de Informática.
    p. 75-82
    Presentation of work at congresses

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  • On improving a pipelined scheduling logic

     Ruben, Gran; Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    XVIII Jornadas de Paralelismo. CEDI 2007 II Congreso Español de Informática.
    p. 1
    Presentation of work at congresses

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  • On Tolerating the Scheduling-Loop Latency

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2007-10
    Report

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  • A comparison of two policies for issuing instructions speculatively

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    Journal of systems architecture
    Vol. 53, num. 4, p. 170-183
    Date of publication: 2007-04
    Journal article

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  • An Enchancement for a Scheduling Logic Pipelined over two Cycles

     Olive Duran, Angel
    Jornadas de Paralelismo
    Presentation's date: 2006-09-18
    Presentation of work at congresses

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  • Non-Speculative Enhancements for a Pipelined Scheduling Logic

     Olive Duran, Angel
    Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2006)
    Presentation's date: 2006-07-26
    Presentation of work at congresses

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  • Predicting L2 Misses to Increase Issue-Queue Efficacy

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    4th Workshop on Memory Performance Issues (WMPI-2006) in conjunction with the 12th International Symposium on High-Performance Computer Architecture (HPCA-12)
    p. 29-35
    Presentation of work at congresses

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  • An Enhancement for a Scheduling Logic Pipelined over two Cycles

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Jornadas de Paralelismo
    p. 1-6
    Presentation of work at congresses

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  • An Enhancement for a Scheduling Logic Pipelined over two Cycles

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    ICCD 2006 XXIV IEEE International Conference on Computer Design
    p. 203-209
    Presentation of work at congresses

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  • Non-Speculative Enhancements for a Pipelined Scheduling Logic

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2006)
    p. 1-4
    Presentation of work at congresses

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  • An Enhancement for a Sceduling Logic Pipelined over two Cycles

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2006-07
    Report

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  • On Tolerating the Scheduling-Loop Latency Non-Speculatively

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2006-07
    Report

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  • Planificador por Niveles de Dependencia

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2006-10
    Report

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  • La Lógica de Lanzamiento a Ejecución de Instrucciones

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2006-10
    Report

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  • A Mechanism for Verifying Data Speculation

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    Euro-Par
    p. 525-534
    Presentation of work at congresses

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  • A Mechanism for Verifying Data Speculation

     Olive Duran, Angel
    Euro-Par
    Presentation's date: 2004-08-31
    Presentation of work at congresses

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  • A Mechanism for Verifying Data Speculation

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    Lecture notes in computer science
    Vol. 1, num. 3149, p. 525-534
    Date of publication: 2004-08
    Journal article

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  • Address Prediction and Recovery Mechanisms  Open access

     Morancho Llena, Enrique
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    Uno de los mayores retos que debe ser afrontado por los diseñadores de micro-procesadores es el de mitigar la gran latencia de las instrucciones de carga de datos en registros. Esta tesis analiza una de las posibles alternativas para atacar dicho problema: predicción de direcciones y ejecución especulativa.Varios autores han comprobado que las direcciones efectivas calculadas por las instrucciones de carga son bastante predecibles. En primer lugar, hemos analizado a qué es debida dicha predictabilidad. Este estudio intenta establecer las estructuras típicas presentes en lenguajes de alto nivel que, al ser compiladas, generas instruciones de carga predecibles. También se analizan los predictores convencionales con el objetivo de determinar qué predictores son más adecuados para las típicas aplicaciones.El estudio continúa con la propuesta de nuevos predictores de direcciones que utilizan sus recursos de almacenamiento de forma más eficiente que los previos predictores. Los predictores alamacenan información respecto al comportamiento de las instrucciones de carga; sin embargo, los requisitos de las instrucciones predecibles son diferentes de los de las instrucciones no predecibles. Consecuentemente, se propone una organización de las tablas de predicción que considere la existencia de ambos tipos de instruciones. También se muestra que existe un cierto grado de redundnacia en las tablas de predicción de los predictores. Este estudio propoen organizar las tablas de predicción de forma que se reduzca dicha redundancia. Todas estas propuestas permiten reducir los requisitos de los predictores referentes a espacio de alamacenamiento, sin causar menoscabo en el rendimiento de los predictores.Posteriormente, se evalúa el impacto de la predicción de direcciones en el rendimiento de los processadores. Las evaluaciones asumen que las predicciones se utilizan para iniciar de forma especulativa accessos a memoria y para ejecutar de forma especulativa sus instrucciones dependientes. En caso de una predicción correcta, todo el trabajo realizado de forma especulativa puede considerarse como correcto; en caso de error de predicción, el tranajo realizado especulativamente debe ser descartado. El estudio se centra en diversos aspectos como la interacción entre predicción de direcciones y predicción de saltos, la implementación de mecanismods de verification, los mecanismos re recuperación en casos de errores de predicción y la influencia de varios parámetreos del procesador (el tamaño de la ventana de emisión de instrucciones, la latencia de la memora cache, y la anchura de emisión de instrucciones) en le impacto de la predicción de direcciones en el rendimiento de los procesadores.Finalmente, se han evaluado mechanismos de recuperación para el caso de errores de predicción de latencia. La predicción de latencia es una técnica de ejecución especulativa utilizada por los planificadores de alguncos procesadores superescalares para tratar las instrucciones de latencia variable (por ejemplo, las instrucciones de carga). Nuestras evaluaciones se centran en un mecanismo convencional de recuperación para errores de predicción de latencia y en una nueva propuesta. También se evalúan los mecanismos propuestos en el ámbito de predicción de direcciones. Se concluye con que éstos mecanismos representan una alternativa rentable a los mecanismos de recuperación convencionales utilizados para tratar los errores de predicción de direcciones.

    Mitigating the effect of the large latency of load instructions is one of challenges of micro-processor designers. This thesis analyses one of the alternatives for tackling this problem: address prediction and speculative execution.Several authors have noticed that the effective addresses computed by the load instructions are quite predictable. First of all, we study why this predictability appears; our study tries to detect the high-level language structures that are compiled into predictable load instructions. We also analyse the conventional address predictors in order to determine which address predictors are most appropriate for the typical applications.Our study continues by proposing address predictors that use their storage structures more efficiently. Address predictors track history information of the load instructions; however, the requirements of the predictable instructions are different from the requirements of the unpredictable instructions. We then propose an organization of the prediction tables considering the existence of both kinds of instructions. We also show that there is a certain degree of redundancy in the prediction tables of the address predictors. We propose organizing the prediction tables in order to reduce this redundancy. These proposals allow us to reduce the area cost of the address predictors without impacting their performance.After that, we evaluate the impact of address prediction on processor performance. Our evaluations assume that address prediction is used to start speculatively some memory accesses and to execute speculatively their dependent instructions. On a correct prediction, all the speculative work is considered as correct; on a misprediction, the speculative work must be discarded. Our study is focused on several aspects such as the interaction of address prediction and branch prediction, the implementation of verification mechanisms, the recovery mechanism on address mispredictions, and the influence of several processor parameters (the issue-queue size, the cache latency and the issue width) on the performance impact of address prediction. Finally, we evaluate several recovery mechanisms for latency mispredictions. Latency prediction is a speculative technique used by the schedulers of some superscalar processors to deal with variable-latency instructions (for instance, load instructions). Our evaluations are focused on a conventional recovery mechanism for latency mispredictions and a new proposal. We also evaluate the proposed recovery mechanism in the scope of address prediction; we conclude that it represents a cost-effective alternative to the conventional recovery mechanisms used for address mispredictions.

  • Recovery Mechanism for Latency Mispredictions

     Olive Duran, Angel
    10th International Conference on Parallel Architectures and Compilation Techniques (PACT'01)
    Presentation's date: 2001-09-08
    Presentation of work at congresses

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  • Recovery Mechanism for Latency Misprediction

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    10th International Conference on Parallel Architectures and Compilation Techniques (PACT'01)
    p. 118-128
    Presentation of work at congresses

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  • Recovery mechanism for latency misprediction

     Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2001-11
    Report

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  • Two-Level Address Storage and Address Prediction

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    Euro-Par
    p. 960-964
    Presentation of work at congresses

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  • Two-Level Address Storage and Address Prediction

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    X Jornadas de Paralelismo
    p. 29-37
    Presentation of work at congresses

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  • Looking at History to Filter Allocations in Prediction Tables

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    8th International Conference on Parallel Architectures and Compilation Techniques (PACT'99)
    p. 314-319
    Presentation of work at congresses

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  • Discrete Last-Address Predictor

     Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 1999-01
    Report

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  • Looking History to Filter Allocations in Prediction Tables

     Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 1999-06
    Report

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  • Two-Level Address Storage and Address Prediction

     Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 1999-10
    Report

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  • Split Last-Address Predictor

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    IX Jornadas de Paralelismo
    p. 275-282
    Presentation of work at congresses

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  • One-Cycle Zero-Offset Loads

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel; Jimenez Castells, Marta
    European Parallel and Distributed Systems (Euro-PDS´98)
    p. 87-93
    Presentation of work at congresses

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  • Split Last Address Predictor

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    International Conference on Parallel Architectures and Compilation Techniques
    p. 230-239
    Presentation of work at congresses

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  • Split Last-Address Predictor

     Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 1998-05
    Report

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  • Reducing the influence of memory access instructions on stall cycles

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel; Jimenez Castells, Marta
    Jornadas de Paralelismo
    p. 161-170
    Presentation of work at congresses

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  • Reducing the influence of Memory Access Instructions on Stall Cycles

     Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.; Jimenez Castells, Marta
    Date: 1997-06
    Report

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  • Introducción a los lenguajes máquina y ensamblador del VAX-II

     Ayguade Parra, Eduard; Borensztjen de Monsegur, Patricia; del Corral González, Anna M.; Gallego Fernandez, M. Isabel; Olive Duran, Angel; Sanchez Carracedo, Fermin; Torres Viñals, Jordi
    Date of publication: 1992-10
    Book

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  • ANÀLISI DE MEMÒRIES CACHE D'INSTRUCCIONS NO CONVENCIONALS.

     Olive Duran, Angel
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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