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  • Pre-bond testing of weak defects in TSVs

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    IEEE International On-Line Testing Symposium
    p. 31-36
    DOI: 10.1109/IOLTS.2014.6873668
    Presentation's date: 2014-07-07
    Presentation of work at congresses

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    Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and may undergo defects during the fabrication process and also during their life time. The detection of defective TSVs in the earliest process step is of major concern. For this reason, testing TSVs is usually done at different stages of the fabrication process. In fact, effective pre-bond testing is a key factor to prevent stacking yield loss. Extensive research effort has been devoted to develop efficient pre-bond techniques. In this direction, two main approaches have been explored: pre-bond probing and built-in self test (BIST) techniques. Pre-bond probing is challenging since TSVs are too small for standard test probes and the number of probe pads for testing is not affordable. Present BIST proposals have some disadvantages depending on the particular solution considered, namely: the detection of certain types of defects solely, inability to detect weak defects, large area overhead and long test application time. In this context, this work proposes a simple solution, adding low area overhead and fast application test procedure. Simulation results confirm the proposal viability. © 2014 IEEE.

  • Post-Bond test of through-silicon vias with open defects

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan
    IEEE European Test Symposium
    p. 1-6
    DOI: 10.1109/ETS.2014.6847816
    Presentation's date: 2014-05-29
    Presentation of work at congresses

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    Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent failure mechanism affecting TSVs. Although there is considerable research effort dedicated to improve TSVs testing, no much attention has been paid to weak defects, especially to weak open defects (resistive opens) causing small delays. In this work, a testing strategy is proposed to detect small delay defects by means of a post-bond oscillation test. Variations in the Duty Cycle of transmitted signals after unbalanced logic gates are shown to detect weak open defects in TSVs. HSPICE simulations including process parameter variations show the effectiveness of the method in the detection of weak open defects above 1 kO.

  • Backside polishing detector

     Manich Bou, Salvador; Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Sigl, Georg; Mujal, Jordi
    Workshop on Trustworthy Manufacturing and Utilization of Secure Devices
    Presentation's date: 2013-12-13
    Presentation of work at congresses

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    Present techniques for attacking secure devices include chip backside reverse engineering. In this presentation a detector sensitive to the removal of silicon backside material is presented. It is based on the side effect of the through silicon bias used for high bandwith communication through silicon die in digital chips.

  • BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    IEEE European Test Symposium
    DOI: 10.1109/ETS.2013.6569389
    Presentation of work at congresses

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    Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects

    built-in self test integrated circuit testing three-dimensional integrated circuits

  • Adaptive self test of defective TSVs

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2012-11-30
    Presentation of work at congresses

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  • Circuito de autotest integrado de TSVs

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date of request: 2012-10-09
    Invention patent

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    La invención presenta un sistema autotest integrado para la detección de defectos en TSVs (Through Silicon Vias o vías a través de silicio) durante la fase pre-bond, durante la cual solo uno de los terminales de la TSV es accesible. En ausencia de un defecto, el sistema evoluciona siempre hacia un mismo estado predefinido. En presencia de un defecto, el sistema evoluciona hacia otro estado diferente del establecido en ausencia de defecto. Esta invención permite a su vez que la misma estructura se utilice para la reconfiguración del circuito al final del proceso de fabricación si el resultado del test determina la presencia de una TSV defectuosa.

  • Integració i avaluació de competències genèriques als Graus de l'ETSEIB  Open access

     Rodríguez Montañés, Rosa; Aguilar Perez, Marta
    Jornada d'Innovació Docent UPC
    p. 1-10
    Presentation's date: 2012-02-07
    Presentation of work at congresses

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  • Integració i avaluació de competències genèriques als Graus de l'ETSEIB

     Rodríguez Montañés, Rosa; Aguilar Perez, Marta
    Jornada d'Innovació Docent UPC
    Presentation's date: 2012-02-07
    Presentation of work at congresses

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  • 8T SRAM Cell with Open Defects under Voltage and Timing Variations

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Castillo Muñoz, Raul
    Conference on Design of Circuits and Integrated Systems
    p. 155-160
    Presentation's date: 2011-11-16
    Presentation of work at congresses

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  • CLIL implementation at a Spanish university: A pilot experience

     Aguilar Perez, Marta; Rodríguez Montañés, Rosa; Oriol, Carlos
    English for International and Intercultural Communication
    p. 31-32
    Presentation's date: 2011-06-03
    Presentation of work at congresses

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  • Impacto de la variabilidad en las estrategias de test y diagnóstico de circuitos micro/nanoelectrónicos

     Balado Suarez, Luz Maria; Sanahuja Moliner, Ricard; Lupon Roses, Emilio Jose; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Manich Bou, Salvador; Vatajelu, Elena Ioana; Arumi Delgado, Daniel; Figueras Pamies, Juan
    Competitive project

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  • Diagnosis of full open defects in interconnect lines with fan-out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-11
    Report

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  • Simulations of interconnect open faults

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-11
    Report

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  • Detectability study of single via opens in a 90nm technology design

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-10
    Report

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  • Defective Behaviour of an 8T SRAM Cell with Open Defects

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Manich Bou, Salvador; Figueras Pamies, Juan; Di Carlo, Stefano; Prinetto, Paolo; Scionti, Alberto
    International Conference on Advances in System Testing and Validation Lifecycle
    p. 81-86
    DOI: 10.1109/VALID.2010.19
    Presentation's date: 2010-08-24
    Presentation of work at congresses

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  • Diagnosis of full open defects in interconnect lines with fan-out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram
    IEEE European Test Symposium
    p. 233-238
    Presentation's date: 2010-05-27
    Presentation of work at congresses

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  • Open defects in nanometer technologies

     Figueras Pamies, Juan; Rodríguez Montañés, Rosa; Arumi Delgado, Daniel
    DOI: 10.1007/978-90-481-3282-9
    Date of publication: 2009-11-01
    Book chapter

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  • Models for Bridging Defects

     Renovell, Michel; Azais, Florence; Figueras Pamies, Juan; Rodríguez Montañés, Rosa; Arumi Delgado, Daniel
    DOI: 10.1007/978-90-481-3282-9
    Date of publication: 2009-11-01
    Book chapter

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  • Qualitat en Electrònica: Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades

     Figueras Pamies, Juan; Carrasco Lopez, Juan Antonio; Lupon Roses, Emilio Jose; Manich Bou, Salvador; Rodríguez Montañés, Rosa; Rius Vazquez, Jose; Balado Suarez, Luz Maria; Ferre Fabregas, Antoni; Suñe Socias, Victor Manuel; Arumi Delgado, Daniel; Sanahuja Moliner, Ricard
    Competitive project

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  • HI2008-0041 Acción integrada de investigación científica y tecnológica entre España e Italia

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Manich Bou, Salvador
    Competitive project

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  • Impact of Gate Leakage Currents on Full Open Defects in SRAM Cells

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2008-11-12
    Presentation of work at congresses

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  • Time-dependent behaviour of full open defects in interconnecting lines

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C; Kruseman, Bram
    INTERNATIONAL TEST CONFERENCE
    p. 1-10
    Presentation's date: 2008-10-29
    Presentation of work at congresses

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  • Enhancement of defect diagnosis based on the analysis of CMOS DUT behaviour  Open access

     Arumi Delgado, Daniel
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    Les dimensions dels transistors disminueixen per a cada nova tecnologia CMOS. Aquest alt nivell d'integració complica el procés de fabricació dels circuits integrats, apareixent nous mecanismes de fallada. En aquest sentit, els mètodes de diagnosi actuals no són capaços d'assumir els nous reptes que sorgeixen per a les tecnologies nanomètriques. A més, la inspecció física de fallades (Failure Analysis) no es pot aplicar des d'un bon començament, ja que els costos de la seva utilització són massa alts. Per aquesta raó, conèixer el comportament dels defectes i dels seus mecanismes de fallada és imprescindible per al desenvolupament de noves metodologies de diagnosi que puguin superar aquests nous reptes. En aquest context, aquesta tesi presenta l'anàlisi dels mecanismes de fallada i proposa noves metodologies de diagnosi per millorar la localització de ponts (bridge) i oberts (open). Per a la diagnosi de ponts, alguns treballs s'han beneficiat de la informació obtinguda durant el test de corrent (IDDQ). No obstant no han tingut en compte l'impacte del corrent de dowsntream. Per aquesta raó, en aquesta tesi s'analitza l'impacte d'aquest corrent degut als ponts i la seva dependència amb la tensió d'alimentació (VDD). A més, es presenta una nova metodologia de diagnosi basada en els múltiples nivells de corrent. Aquesta tècnica considera els corrents generats per les diferents xarxes connectades pel pont. Aquesta metodologia s'ha aplicat amb èxit a un conjunt de xips defectuosos de tecnologies de 0.18 µm i 90 nm.Com alternativa a les tècniques basades en corrent, els shmoo plots també poden ser útils per a la diagnosi. Tradicionalment s'ha considerat que valors baixos de VDD són més apropiats per a la detecció de ponts. Tanmateix es demostra en aquesta tesi que en presència de ponts connectant xarxes equilibrades, valors alts de VDD són fins i tot més apropiats que tensions baixes, amb la conseqüent implicació que això té per a la diagnosi.En relació als oberts, s'ha dissenyat i fabricat un xip amb la inclusió intencionada d'oberts complets (full opens) i oberts resistius. Experiments fets amb els xips demostren l'impacte de les capacitats d'acoblament de les línies veïnes. A més, pels oberts resistius s'ha comprovat la influència de l'efecte història i de la localització de l'obert en el retard. Tradicionalment s'ha considerat que el retard màxim s'obté quan un obert resistiu es troba al principi de la línia. No obstant això no es pot generalitzar a oberts poc resistius, ja que en aquests casos es demostra que el màxim retard s'obté per a una localització intermèdia. A partir dels resultats experimentals obtinguts amb el xip, s'ha desenvolupat una nova metodologia per a la diagnosi d'oberts complets a les línies d'interconnexió. Aquest mètode divideix la línia en diferents segments segons la informació de layout de la pròpia línia. Aleshores coneixent els valors de les línies veïnes, es prediu la tensió del node flotant, la qual es compara amb el resultat experimental obtingut a la màquina de test. Aquest mètode s'ha aplicat amb èxit a un seguit de xips defectuosos pertanyents a una tecnologia de 0.18 µm.Finalment, s'ha analitzat l'impacte que tenen els corrents de túnel a través del terminal de porta en presència d'un obert complet. Com les dimensions disminueixen per a cada nova tecnologia, l'òxid de porta és suficientment prim com per generar corrents de túnel que influencien el node flotant. Aquests corrents generen una evolució temporal al node flotant fins fer-lo arribar a un estat quiescent, el qual depèn de la tecnologia. Es comprova que aquestes evolucions temporals són de l'ordre de segons per a una tecnologia de 0.18 µm. Tanmateix les simulacions demostren que aquests temps disminueixen fins a uns quants µs per a tecnologies futures. Degut a l'impacte dels corrents de túnel, un seguit d'oberts complets s'han diagnosticat en xips de 0.18 µm.

    Transistor dimensions are scaled down for every new CMOS technology. Such high level of integration has increased the complexity of the Integrated Circuits (ICs) manufacturing process, arising new complex failure mechanisms. However, present diagnosis methodologies cannot afford the challenges arisen for future technologies. Furthermore, physical failure analysis, although indispensable, is not feasible on its own, since it requires high cost equipment, tools and qualified personnel. For this reason, a detailed understanding and knowledge of defect behaviours is a key factor for the development of improved diagnosed methodologies to overcome the challenges of nanometer technologies. In this context, this thesis presents the analysis of existing and new failure mechanisms and proposed new diagnosis methodologies to improve the diagnosis of faults, focused on bridging and open faults.IDDQ is a well known technique for the diagnosis of bridging faults. However, previous works have not considered the impact of the downstream current for the diagnosis of such faults. In this thesis, the impact and the dependence of the downstream current with the power supply voltage (VDD) is analyzed and experimentally measured. Furthermore, a multiple level IDDQ based diagnosis technique is presented. This method takes benefit from the currents generated by the different network excitations. This technique is successfully applied to real defective devices from 0.18 µm and 90 nm technologies.As an alternative to current based techniques, shmoo plots can be also useful for diagnosis purposes. Low voltage has been traditionally considered as an advantageous condition for the detection of bridging faults. However, it is demonstrated that in presence of bridges connecting balanced n- and p-networks, high VDD values are also advantageous for the detection of bridges, which has its direct translation into diagnosis application. Experimental evidence of this fact is presented.Related to open faults, an experimental chip has been designed and fabricated in a 0.35 µm technology, where full and resistive open defects have been intentionally added. Different experiments have been carried out so that the impact of the neighbouring coupling capacitances has been quantified. Furthermore, for resistive opens, experiments have demonstrated the influence of the history effect and the location of the defect on the delay. Traditionally, it has been reported that the highest delay is obtained when the resistive open is located at the beginning of the net. Nevertheless, this thesis demonstrates that this is not true for low resistive open, since the highest delay is obtained for an intermediate location. Experimental measurements prove this behaviour.Derived from the results obtained with the fabricated chip, a new methodology for the diagnosis of interconnect full open defects is developed. The FOS (Full Open Segment) method divides the interconnect line into different segments based on the topology of the faulty line. Knowing the logic state of the neighbouring lines, the floating net voltage is predicted and compared with the experimental results obtained on the tester. This method has been successfully applied to a set of 0.18 µm defective devices. Finally, the impact of the gate tunnelling leakage currents on the behaviour of full open defects has also been analyzed. As technology dimensions are scaled down, the oxide thickness is thin enough so that the gate tunnelling leakage currents influence the behaviour of floating lines. They cause transient evolutions on the floating node until reaching the steady state, which is technology dependent. It is experimentally demonstrated that these evolutions are in the order of seconds for a 0.18µm technology. However, for future technologies, simulations show that the evolutions decrease down to a few µs. Based on this factor, some full open faults present in 0.18 µm technology devices are diagnosed.

  • VTS07 Best Paper Award

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Rodríguez-Montañés, R; Eichenberger, Stefan; Hora, C; Kruseman, Bram; Lousberg, M; Majhi, A K
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  • Impact of Gate Tunnelling Leakage on CMOS Circuits with Full Open Defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2007-11-22
    Presentation of work at congresses

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  • TEC2007-66672 DIAGNOSTICO EN TECNOLOGIAS CMOS NANOMETRICAS: MEJORA DEL RENDIMIENTO

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Lupon Roses, Emilio Jose; Manich Bou, Salvador; Rius Vazquez, Jose; Balado Suarez, Luz Maria
    Competitive project

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  • Caracterización eléctrica de planos de tintas conductoras sobre tejidos: modelo y datos experimentales.

     Rius Vazquez, Jose; Palacín, M; Casadevall, V; Rodríguez Montañés, Rosa; Manich Bou, Salvador; Ridao Granado, Miguel
    Date: 2007-06
    Report

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  • Caracterización de la respuesta estática del proceso de impresión de pistas conductoras por serigrafía en función de la anchura y espaciado entre líneas

     Rodríguez Montañés, Rosa; Casadevall, V; Rius Vazquez, Jose; Manich Bou, Salvador; Ridao Granado, Miguel
    Date: 2007-06
    Report

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  • Access to the full text
    Diagnosis of full open defects in interconnecting lines  Open access

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram; Lousberg, M.; Majhi, A.K.
    IEEE VLSI Test Symposium
    p. 1-6
    DOI: 10.1109/TEST.2008.4700575
    Presentation's date: 2007-05-07
    Presentation of work at congresses

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    A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.

    Best Paper Award al millor article del congrés IEEE VLSI Test Symposium 2007

  • Process-variability aware delay fault testing of ·VT and weak-open defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Pineda de Gyvez, José; Gronthoud, G
    The Eighth IEEE European Test Workshop
    p. 85-90
    Presentation's date: 2007-05-27
    Presentation of work at congresses

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  • Diagnosis of Bridging Defects Based On Current Signatures at Low Power Supply Voltages

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Einchenberger, S; Hora, C; Kruseman, Bram; Lousberg, M; Majhi, A K
    IEEE VLSI Test Symposium
    p. 145-150
    Presentation's date: 2007-05-07
    Presentation of work at congresses

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  • Validación del ancho de banda de las líneas de transmissión textiles M133 a M137

     Manich Bou, Salvador; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Casadevall, V; Ridao Granado, Miguel
    Date: 2007-02
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  • Análisis de la sensibilidad y estabilidad de los teclados textiles M125, M127, M129, M131

     Manich Bou, Salvador; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Casadevall, V; Ridao Granado, Miguel
    Date: 2007-02
    Report

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  • Electrical Characterization of Conductive Ink Layers on Textile Fabrics: Model and Experimental Results

     Rius Vazquez, Jose; Manich Bou, Salvador; Rodríguez Montañés, Rosa; Ridao, Miquel
    XXII Conference of Circuits and Integrated Systems
    p. 1-6
    Presentation of work at congresses

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  • Letter of the Month

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Rodríguez-Montañés, R; Eichenberger, Stefan; Hora, C; Kruseman, Bram
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  • Estudio de la Calidad y Estabilidad de las Tintas A, B y C como Medio de Alimentación Elèctrica de Circuitos Integrados

     Manich Bou, Salvador; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Casadevall, V y M Ridao; Ridao Granado, Miguel
    Date: 2006-12
    Report

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  • Experimental Characterization of CMOS Interconnect Open Defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2006-11-22
    Presentation of work at congresses

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  • Full open segment model in interconnecting lines

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2006-09-01
    Report

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  • Diagnosis of bridging defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2006-07-03
    Report

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  • Classification of defective Veqtor4 devices under different stress test conditions

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2006-05-02
    Report

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  • Lissajous Based Mixed-Signal Testing for N-Observable Signals

     Balado Suarez, Luz Maria; Lupon Roses, Emilio Jose; Rodríguez Montañés, Rosa; García, L; Figueras Pamies, Juan
    2006 IEEE DESIGN AND DIAGNOSTIC OF ELECTRONIC CIRCUITS AND SYSTEMS
    p. 125-130
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  • Defective Behaviours of Resistive Opens in Interconnect Lines

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    10th European Test Symposium
    p. 28-33
    Presentation's date: 2005-05-23
    Presentation of work at congresses

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  • Electrical and topological characterization of interconnect open defects

     Rodríguez Montañés, Rosa; Figueras, J
    International Workshop on Current and Defect Based Testing, 2005. DBT 2005.
    p. 42-46
    Presentation of work at congresses

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  • TEC2004-02625 AUTOTEST Y DIAGNOSTICO DE CIRCUITOS Y SISTEMAS INTEGRADOS HETEROGENEOS EN TECNOLOGIAS CMOS NANOMETRICAS

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Lupon Roses, Emilio Jose
    Competitive project

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  • Improving the Efficiency of Arithmetic BIST by Combining Targeted

     Manich Bou, Salvador; García, L; Balado Suarez, Luz Maria; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    p. 901-906
    Presentation's date: 2004-11-24
    Presentation of work at congresses

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  • Testing of RF Systems by Zoning the Constellation Diagram

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation of work at congresses

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  • BIST Technique by Equally Spaced Test Vector Sequences (http://ieeexplore.ieee.org/iel5/9095/28867/01299245.pdf)

     Manich Bou, Salvador; García, L; Balado Suarez, Luz Maria; Lupon Roses, Emilio Jose; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    IEEE VLSI Test Symposium
    p. 206-211
    Presentation's date: 2004
    Presentation of work at congresses

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  • Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results

     Rius Vazquez, Jose; Manich Bou, Salvador; Rodríguez Montañés, Rosa; JOSEP, RIUS; Alejandro, Peidro
    Date of publication: 2003-09
    Book chapter

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  • Access to the full text
    A Combinatorial method for the evaluation of yield of Fault-tolerant systems-on-chip  Open access

     Suñe Socias, Victor Manuel; Rodríguez Montañés, Rosa; Carrasco Lopez, Juan Antonio; Munteanu, D-P
    IEEE/IFIP International Conference on Dependable Systems and Networks
    p. 563-572
    Presentation's date: 2003
    Presentation of work at congresses

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    In this paper we develop a combinatorial method for the evaluation of yield of fault-tolerant systems-on-chip. The method assumes that defects are produced according to a model in which defects are lethal and affect given components of the system following a distribution common to all defects. The distribution of the number of defects is arbitrary. The method is based on the formulation of the yield as 1 minus the probability that a given boolean function with multiple-valued variables has value 1. That probability is computed by analyzing a ROMDD (reduced ordered multiple-valuedecision diagram) representation of the function. For efficiency reasons, we first build a coded ROBDD (reduced ordered binary decision diagram) representation of the function and then transform that coded ROBDD into the ROMDD required by the method. We present numerical experiments showing that the method is able to cope with quite large systems in moderate CPU times.