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  • Efficient multiprocessing architectures for Spiking Neural Network emulation based on configurable devices

     Sanchez Rivera, Giovanny
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    L'estudi de la dinàmica de les xarxes neuronals bio-inspirades ha permès als neurocientífics entendre alguns processos i estructures del cervell . Les implementacions electròniques d'aquestes xarxes neuronals són eines útils per dur a terme aquest tipus d'estudi . No obstant això, l'alta complexitat de les xarxes neuronals requereix d'una arquitectura apropiada que pugui simular aquest tipus de xarxes. Emular aquest tipus de xarxes en dispositius configurables és possible a causa del seu extraordinari desenvolupament respecte a la seva disponibilitat de recursos, velocitat i capacitat de reconfiguració (FPGAs ) .En aquesta tesi es proposa una arquitectura maquinari paral · lela i configurable per emular les complexes i realistes xarxes neuronals tipus spiking en temps real . S'han estudiat i analitzat alguns models de neurones tipus spiking rellevants i les seves implementacions en maquinari , amb la finalitat de crear una arquitectura que suporti la implementació d'aquests models de manera eficient .S'han tingut en compte diversos factors clau, incloent flexibilitat en la programació d'algorismes, processament d'alt rendiment, baix consum d'energia i àrea. S'han aplicat diverses tècniques en l'arquitectura desenvolupada amb el propòsit d'augmentar la seva capacitat de processament. Aquestes tècniques són: mapejat de temps a espai, virtualització de les neurones, mapeig flexible de neurones i sinapsis, modes d'execució, i aprenentatge específic, entre d'altres. A més, s'ha desenvolupat una unitat d'interfície de dades per tal de construir un sistema bio-inspirat, que pot processar informació sensorial del medi ambient. Aquest sistema basat en neurones tipus spiking combina implementacions analògiques i digitals. S'han desenvolupat diverses aplicacions usant aquest sistema com a prova de concepte, per tal de mostrar les capacitats de l'arquitectura proposada per al processament d'aquest tipus d'informació.

  • Centre d'Estudis Tecnològics per a l'atenció a la Dependència i vida autònoma

     Cabestany Moncusi, Joan; Català Mallofré, Andreu; Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi; Cosp Vilella, Jordi; Llanas Parra, Francesc Xavier; Sama Monsonis, Albert; Perez Lopez, Carlos; Rodriguez Martin, Daniel Manuel; Reyes Ortiz, Jorge Luis; Sayeed, Taufique; Takac, Boris; Khan, Rafiullah; Huang-Ming, Chang; Bano, Sophia
    Competitive project

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  • Quasi-digital front-ends for current measurement in integrated circuits with giant magnetoresistance technology

     De Marcellis, A.; Cubells Beltrán, M. Dolores; Reig Escriva, Abilio Càndid; Madrenas Boadas, Jordi; zadov, Boris; Paperno, Eugene; Cardoso, S.; Freitas, P.P.
    IET circuits, devices and systems
    Vol. 8, num. 4, p. 291-300
    DOI: 10.1049/iet-cds.2013.0348
    Date of publication: 2014-07-01
    Journal article

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    In this study, the authors report on two different electronic interfaces for low-power integrated circuits electric current monitoring through current-to-frequency (I-f) conversion schemes. This proposal displays the intrinsic advantages of the quasi-digital systems regarding direct interfacing and self-calibrating capabilities. In addition, as current-sensing devices, they have made use of the giant magnetoresistance (GMR) technology because of its high sensitivity and compatibility with standard complementary metal oxide semiconductor processes. Single elements and Wheatstone bridges based on spin-valves and magnetic tunnel junctions have been considered. In this sense, schematic-level simulations for integration in Austria Microsystems 0.35 mu m technology have been corroborated by means of experimental measurements with the help of printed circuit board prototypes and real GMR devices. Tables with relevant parameters (silicon area, power consumption, sensitivity etc.) have been constructed as practical tools for designers. Electric currents down to 2 mu A have been resolved in this way.

  • Realistic model of compact VLSI FitzHugh-Nagumo oscillators

     Cosp Vilella, Jordi; Binczak, Stéphane; Madrenas Boadas, Jordi; Ruiz Fernández, Daniel
    International journal of electronics
    Vol. 101, num. 2, p. 220-230
    DOI: 10.1080/00207217.2013.780263
    Date of publication: 2014-02-01
    Journal article

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    In this article, we present a compact analogue VLSI implementation of the FitzHugh-Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off frequency. Post-layout simulations for a CMOS 0.35 m double-poly technology using the MOSFET Spice BSIM3v3 model confirm the proper behaviour of the design. © 2013 Taylor & Francis.

  • An asynchronous finite-state-machine-based buck-boost converter for on-chip adaptive power supply

     Fernández, Daniel; Madrenas Boadas, Jordi; Alarcon Cot, Eduardo Jose
    Analog integrated circuits and signal processing
    Vol. 74, num. 1, p. 227-238
    DOI: 10.1007/s10470-012-9975-8
    Date of publication: 2013-01
    Journal article

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    In this paper we present an asynchronous finite-state machine digital controller co-integrated with an on-chip non-inverting buck-boost power converter with dynamic signal-tracking capabilities. The mostly-digital controller functionally implements a non-PWM zone-wise control law through asynchronous circuitry, thus exhibiting self-timed minimum latency and ultra low power operation due to gate switching activity. Experimental results on a 0.35 µm CMOS technology demonstrate an efficiency up to 80 % with a switching frequency of 2.86 MHz.

    In this paper we present an asynchronous finite-state machine digital controller co-integrated with an on-chip non-inverting buck-boost power converter with dynamic signal-tracking capabilities. The mostly-digital controller functionally implements a non-PWM zone-wise control law through asynchronous circuitry, thus exhibiting self-timed minimum latency and ultra low power operation due to gate switching activity. Experimental results on a 0.35 lm CMOS technology demonstrate an efficiency up to 80 % with a switching frequency of 2.86 MHz

  • Spike-based analog-digital neuromorphic information processing system for sensor applications

     Sánchez Rivera, Giovanny; Koickal, Thomas Jacob; Sripad T A, Athul; Gouveia, Luiz Carlos; Hamilton, Alister; Madrenas Boadas, Jordi
    IEEE International Symposium on Circuits and Systems
    p. 1624-1627
    DOI: 10.1109/ISCAS.2013.6572173
    Presentation's date: 2013-05
    Presentation of work at congresses

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    A spiking-neuron-based system that combines analog and digital multi-processor implementations for the bio-inspired processing of sensors is reported. This combination allows creating a powerful bio-inspired multiple-input sensor processing system for environment perception applications. The analog front-end encodes the input signal in a signed spike representation, which is further processed by means of a digital Spiking Neural Network (SNN) on a Single-Instruction Multiple-Data (SIMD) multiprocessor. The spike distribution for both systems is based on Address-Event Representation (AER) scheme, asynchronous for the Analog Pre-Processor (APP) and synchronous for the Digital Multi-Processor (DMP), synchronized by means of an AER transceiver. A proof-of-concept application of the system being able to process sensory information has been demonstrated. The system utilizes 30-neurons emulated by the DMP to process spike-encoded information provided by its analog counterpart, enabling the feature extraction of the input signal. The frequency detection capability of the system is experimentally reported.

  • Quasi-digital conversion for resistive devices: application in GMR-based IC current sensors

     Reig Escriva, Abilio Càndid; Cubells Beltrán, M. Dolores; De Marcellis, A.; Madrenas Boadas, Jordi; Cardoso, S.; Freitas, P.P.
    Spanish Conference on Electron Devices
    p. 135-138
    DOI: 10.1109/CDE.2013.6481361
    Presentation's date: 2013-02
    Presentation of work at congresses

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    Resistive devices, including sensors, are used in a huge range of applications within different scenarios. When a complete system is considered, a quasi-digital output is often recommendable. If the conversion is operated at device level, some problems such as noise disturbs, insertion losses and so on, can be reduced. In this work, we describe a resistance-to-frequency (R-f) converter with a suggested application in low current monitoring by means of GiantMagnetoResistance (GMR) sensors. Specific devices have been designed and microfabricated. The system has been tested by means of discrete components with a PCB. The complete microsystem monolithic integration in a standard CMOS technology has been also analyzed

    Resistive devices, including sensors, are used in a huge range of applications within different scenarios. When a complete system is considered, a quasi-digital output is often recommendable. If the conversion is operated at device level, some problems such as noise disturbs, insertion losses and so on, can be reduced. In this work, we describe a resistance-tofrequency (R-f) converter with a suggested application in low current monitoring by means of GiantMagnetoResistance (GMR) sensors. Specific devices have been designed and microfabricated. The system has been tested by means of discrete components with a PCB. The complete microsystem monolithic integration in a standard CMOS technology has been also analyzed.

  • Sistema en chip micro-electro-mecánico (MEMSOC)

     Cosp Vilella, Jordi; Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi
    Competitive project

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  • Graphical representation of data for a multiprocessor array emulating spiking neural networks

     Sokolnicki, A.; Sanchez Rivera, Giovanny; Madrenas Boadas, Jordi; Moreno Arostegui, Juan Manuel; Sakowicz, B.
    Przeglad elektrotechniczny
    Vol. 88, num. 11, p. 332-336
    Date of publication: 2012
    Journal article

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  • Result-consistent counter sampling scheme for coarse-fine TDCs

     Michalik, Piotr Jozef; Fernandez, D.; Madrenas Boadas, Jordi
    Electronics Letters
    Vol. 48, num. 19, p. 1195-1196
    DOI: 10.1049/el.2012.1465
    Date of publication: 2012-09-13
    Journal article

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  • A translinear, log-domain FPAA on standard CMOS technology

     Fernández, Daniel; Martínez-Alvarado, Luís; Madrenas Boadas, Jordi
    IEEE journal of solid-state circuits
    Vol. 47, num. 2, p. 490-503
    DOI: 10.1109/JSSC.2011.2170597
    Date of publication: 2012-02
    Journal article

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    A field-programmable analog array (FPAA) using a standard-CMOS wide-dynamic-range translinear element (TE) is introduced. The FPAA configurable analog blocks (CABs) are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear and log-domain circuit design. The interfacing is provided by an I/O programmable cell, which allows for easier connectivity between the signal-processing core and the external circuitry. As a proof-of-concept, a 5 $times$ 5 RTC FPAA testchip was implemented in 0.35- $mu{hbox {m}}$ CMOS technology. A set of various circuit primitives, such as one- and four-quadrant multipliers, an Euclidean distance operator and a fourth-order log-domain filter, were mapped on the chip in order to demonstrate the versatility of the approach. FPAA bandwidth reaches 20 MHz with a power consumption of 30 $muhbox{W/TE}$ and precision errors below 3%.

  • Pulsed digital oscillators for electrostatic MEMS

     Gorreta Marine, Sergio; Ruiz Fernández, Daniel; Blokhina, Elena; Pons Nin, Joan; Jimenez Serres, Vicente; O'Connell, D.; Feely, Orla; Madrenas Boadas, Jordi; Dominguez Pumar, Manuel M.
    IEEE transactions on circuits and systems I: regular papers
    Vol. 59, num. 12, p. 2835-2845
    DOI: 10.1109/TCSI.2012.2206459
    Date of publication: 2012
    Journal article

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    This paper introduces a new actuation scheme for implementing Pulsed Digital Oscillators (PDOs) for electrostatic MEMS resonators. In this scheme, the capacitance of the device is biased with a voltage and it is periodically sampled. Short pulses of zero voltage are applied depending on the decisions taken by the oscillator loop. The paper discusses in detail the implementation of such electrostatic PDO (e-PDO) through a prototype and links the e-PDO to the conventional PDO theory. As an example, it is shown that with this actuation scheme it is possible to excite different resonances of the mechanical structure simply by changing the parameters of the feedback filter of the oscillator.

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    Sense/drive architecture for CMOS-MEMS accelerometers with relaxation oscillator and TDC  Open access

     Michalik, Piotr Jozef; Madrenas Boadas, Jordi; Fernandez Martinez, Daniel
    IEEE International Conference on Electronics, Circuits and Systems
    p. 937-940
    DOI: 10.1109/ICECS.2012.6463507
    Presentation's date: 2012-12-10
    Presentation of work at congresses

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  • LCMOS: Light-powered standard CMOS circuits

     Madrenas Boadas, Jordi; Fernandez Martinez, Daniel; Wang, Chunyan
    IEEE International Symposium on Circuits and Systems
    p. 3029-3032
    DOI: 10.1109/ISCAS.2012.6271957
    Presentation's date: 2012-05-21
    Presentation of work at congresses

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    LCMOS, a harvest-use light-powered scheme for standard CMOS circuits based on photogenerated currents in the drain-substrate PN junction of both PMOS and NMOS transistors is introduced. PMOS and NMOS bulks are groundconnected so the generated currents induce symmetrical positive and negative voltage at the PMOS and NMOS sources, respectively. Applying this approach to a CMOS inverter ring oscillator in 150 nm technology, simulations show that nearly 1 Vpp signal range can be obtained. The operation of a simple 4- bit counter is also illustrated. The light-powering technique can be applied almost directly to digital standard cells in ultra-lowpower applications with modest processing speed requirements.

  • A self-test and dynamics characterization circuit for MEMS electrostatic actuators

     Fernandez Martinez, Daniel; Madrenas Boadas, Jordi; Cosp Vilella, Jordi
    Microelectronics reliability
    Vol. 51, num. 3, p. 602-609
    DOI: 10.1016/j.microrel.2010.09.027
    Date of publication: 2011-03
    Journal article

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    This paper presents a high-bandwidth capacitance estimation and driving circuit especially tailored for its use with MEMS electrostatic actuators. The circuit can be integrated as a part of a system comprising an electrostatic actuator to provide self-testing and failure prediction capabilities and also as a simple and low-cost actuator dynamics characterization system capable of measuring both periodic and nonperiodic movements.

  • Modelado de sistemas reconfigurables en señal mixta y aquitecturas con elementos translineales

     Martinez Alvarado, Luis Arturo
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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  • Continuous-time CMOS adaptive asynchronous sigma-delta modulator approximating low-fs low-inband-error on-chip wideband power amplifier

     Alarcon Cot, Eduardo Jose; Fernández, Diego; Garcia Tormo, Albert; Madrenas Boadas, Jordi; Poveda Lopez, Alberto
    IEEE International Symposium on Circuits and Systems
    p. 301-304
    DOI: 10.1109/ISCAS.2011.5937561
    Presentation's date: 2011-05-15
    Presentation of work at congresses

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    A mixed-signal continuous-time-processing standard CMOS implementation of an asynchronous sigma-delta modulator aimed to drive a switching amplifier operating as an on-chip wideband adaptive power supply is presented in this work. The paper first briefly discusses the fundamental limit tracking capabilities of a two-level switching signal to inband-error-free track a bandlimited signal with minimum average switching frequency. It is argued the adequacy of an adaptive asynchronous sigma-delta modulator (AAΣΔ) to approximate such fundamental characteristics. The second part of the paper presents mixed-signal design details of the various subcircuits implementing a CMOS low-power digitally-programmable AAΣΔ modulator, with 7 MHz average switching frequency operation and 1000 µm × 640 µm area occupancy.

  • Bioinspired sensory integration for environment-perception embedded systems

     Madrenas Boadas, Jordi; Fernandez Martinez, Daniel; Cosp Vilella, Jordi; Moreno Arostegui, Juan Manuel; Martínez Alvarado, Luis Arturo; Sanchez Rivera, Giovanny
    International Conference on Biomedical Electronics and Devices
    p. 260-267
    Presentation of work at congresses

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  • Radiation tolerant analogue mixed signal

     Cosp Vilella, Jordi; Madrenas Boadas, Jordi; Fernandez Martinez, Daniel
    Competitive project

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  • Front-end readout ASIC technology study

     Cosp Vilella, Jordi; Madrenas Boadas, Jordi; Fernandez Martinez, Daniel
    Competitive project

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  • Performance evaluation and scaling of a multiprocessor architecture emulating complex SNN algorithms

     Sanchez Rivera, Giovanny; Madrenas Boadas, Jordi; Moreno Arostegui, Juan Manuel
    Lecture notes in computer science (Online)
    Vol. Special ICES 2010, num. 6274, p. 145-156
    DOI: 10.1007/978-3-642-15323-5_13
    Date of publication: 2010-09
    Journal article

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    The performance analysis of an efficient multiprocessor architecture that allows accelerating the emulation of large-scale Spiking Neural Networks (SNNs) is reported. After describing the architecture and the complex SNN algorithm mapping, the performance study demonstrates that the system can emulate up to 10,000 300-synapse neurons in real time at 64 MHz with conventional FPGAs. Important improvements can be achieved by using advanced technology and increased clock rate or by means of simple architecture modifications. The architecture is flexible enough to be efficiently applied to any SNN model in general.

  • Implementation of a power-aware dynamic fault tolerant mechanism on the ubichip platform

     Kobayashi, Kotaro; Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi
    Lecture notes in computer science
    Vol. LNCS Special ICES 2010, p. 299-309
    DOI: 10.1007/978-3-642-15323-5_26
    Date of publication: 2010-09
    Journal article

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  • Experiments on the Release of CMOS-Micromachined Metal Layers

     Fernandez Martinez, Daniel; Madrenas Boadas, Jordi
    Journal of sensors
    Vol. 2010, num. 937301, p. 1-7
    DOI: 10.1155/2010/937301
    Date of publication: 2010
    Journal article

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    JubiTool: Unified design flow for the perplexus SIMD hardware accelerator  Open access

     Brousse, O.; Guillot, J.; Gil, T.; Grize, F.; Sassatelli, G.; Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi; Villa, A.; Volken, H.; Robert, M.
    IEEE Congress on Evolutionary Computation
    p. 2070-2075
    Presentation's date: 2010-02-19
    Presentation of work at congresses

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    This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous computing. This contribution relies on the JubiTool: a set of integrated tools (JubiSplitter, JubiCompiler, UbiAssembler), allowing respectively to extract, compile and assemble parallelizable parts of applications described in Jubi language. Jubi is a modified Java agent based language (JADE) dedicated to the Ubichip (the bio-inspired chip developed within the confines of the Perplexus project). By appending hardware directives to a software agent description, the inherent flexibility of software is combined with the runtime performance of a hardware execution. In the case of typical Perplexus applications such as the Spiking Neural Network Simulator, this contribution takes profit of the intrinsic property of the Ubichip in terms of parallelism resulting in an expected speedup of at least one order of magnitude. Finally, this hybrid (SW/HW) flow could be easily modified and adapted to support other kind of distributed platforms

  • A low-voltage current sorting circuit based on 4-T min-max CMOS switch

     Madrenas Boadas, Jordi; Fernandez Martinez, Daniel; Cosp Vilella, Jordi
    IEEE International Conference on Electronics, Circuits and Systems
    p. 351-354
    DOI: 10.1109/ICECS.2010.5724525
    Presentation's date: 2010-12
    Presentation of work at congresses

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  • DESARROLLO Y EVALUACIÓN DE UN MÉTODO PARA PRODUCIR DISPOSITIVOS MEMS EN UN PROCESO CMOS ESTÁNDARD

     Fernandez Martinez, Daniel; Madrenas Boadas, Jordi
    Competitive project

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  • Translinear signal processing circuits in standard CMOS FPAA

     Martínez-Alvarado, Luis; Madrenas Boadas, Jordi; Fernandez Martinez, Daniel
    2009 IEEE International Conference on Electronics Circuits and Systems
    p. 715-718
    Presentation's date: 2009-12-13
    Presentation of work at congresses

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  • Synchronous digital implementation of the AER communication scheme for emulating large-scale spiking neural networks models

     Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi; Kotynia, L.
    NASA/ESA Conference on Adaptive Hardware and Systems
    p. 189-196
    Presentation of work at congresses

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  • SpiNDeK: An integrated design tool for the multiprocessor emulation of complex bioinspired spiking neural networks

     Hauptvogel, Michael; Madrenas Boadas, Jordi; Moreno Arostegui, Juan Manuel
    IEEE Congress on Evolutionary Computation
    p. 142-148
    Presentation of work at congresses

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    SpiNDeK (Spiking Neural Network Design Kit) is an integrated design tool intended to support the development of emulation of complex bioinspired neural networks. In this work, the most relevant aspects of the tool are reported, regarding the generation of connections as well as synapse and neuron parameters of spiking neural networks as well as the automated code generation and simulation, ready to be executed by an ad-hoc parallel architecture. The tool is fully functional and has demonstrated its usefulness.

  • Self-controlled 4-transistor low-power min-max current selector

     Madrenas Boadas, Jordi; Fernandez Martinez, Daniel; Cosp Vilella, Jordi; Martínez Alvarado, Luis Arturo; Alarcon Cot, Eduardo Jose; Vidal Lopez, Eva Maria; Villar Pique, Gerard
    AEU: international journal of electronics and communications
    Vol. 63, num. 10, p. 871-876
    DOI: 10.1016/j.aeue.2009.07.002
    Date of publication: 2009-10
    Journal article

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  • A Reconfigurable Architecture for Emulating Large-Scale Bio-inspired Systems

     Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi
    IEEE Congress on Evolutionary Computation
    Presentation's date: 2009-05-18
    Presentation of work at congresses

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  • Strategies in SIMD computing for complex neural bioinspired applications

     Madrenas Boadas, Jordi; Moreno Arostegui, Juan Manuel
    NASA/ESA Conference on Adaptive Hardware and Systems
    p. 376-381
    Presentation's date: 2009-08-01
    Presentation of work at congresses

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  • Implementation of a dynamic fault-tolerance scaling technique on a self-adaptive hardware architecture

     Soto Vargas, J.; Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi; Cabestany Moncusi, Joan
    International Conference on ReConFigurable Computing and FPGAs
    p. 445-450
    Presentation of work at congresses

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  • Implementation of a dynamic fault-tolerance scaling technique on a self-adaptative hardware architecture

     Soto Vargas, J.; Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi; Cabestany Moncusi, Joan
    2009 International Conference on ReConFigurable Computing and FPGAs
    p. 445-450
    Presentation of work at congresses

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  • Arquitecturas y circuitos CMOS para el control, generación y procesado de señal de MEMS  Open access

     Fernandez Martinez, Daniel
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    En esta tesis se muestran arquitecturas y circuitos CMOS para el control de actuadores electroestáticos MEMS y para la generación y procesado de las señales proveniente de microsistemas. En el primer capítulo se introducen dos circuitos para la estimación de distancia o capacidad entre armaduras de actuadores electroestáticos y se muestran aplicaciones de los mismos, incluyendo la caracterización de la estática y dinámica de los actuadores, la detección de fallos y envejecimiento y su aplicación dentro de osciladores digitales pulsados y como parte de un sistema de actuación resonante de baja tensión. En el segundo capítulo se muestra un estudio sobre la viabilidad de la fabricación monolítica de actuadores electroestáticos dentro del proceso CMOS utilizando un sencillo proceso de wet etching de bajo coste para liberar las estructuras. En el tercer capítulo se presentan dos elementos translineales CMOS de alto ancho de banda y alta precisión y su aplicación como multiplicadores, divisores, filtros y como parte integrante de una celda reconfigurable con la que construir una FPAA capaz de realizar numerosas funciones del procesado analógico de señal. En el cuarto capítulo se muestran diseños adicionales como una ley para el control de la dinámica de actuadores electroestáticos con la que se pueden ajustar eléctricamente todos los parámetros que gobiernan su movimiento y un convertidor de potencia integrado con control digital basado en una máquina de estados asíncrona. Finalmente, en el capítulo cinco, se presentan las conclusiones finales de este trabajo.

  • Implementation of Compact VLSI FitzHugh-Nagumo Neurons

     Cosp Vilella, Jordi; Binczak, Stéphane; Madrenas Boadas, Jordi; Fernández, D
    IEEE International Symposium on Circuits and Systems
    p. 2370-2373
    Presentation of work at congresses

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  • Diseño de un Multiprocesador Configurable y de la Interfaz de Comunicaciones para una Arquitectura de Hardware Auto-Adaptable

     Vargas, Soto J; Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi; Cabestany Moncusi, Joan
    JCRA 08 - VIII Jornadas de Computación Reconfigurable y Aplicaciones
    p. 295-305
    Presentation of work at congresses

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  • Communication Infrastructure for a Self-Adaptive Hardware Architecture

     Soto, J; Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi; Cabestany Moncusi, Joan
    Reconfigurable Communication-centric Systems-on-Chip workshop 2008 - ReCoSoC'08
    p. 175-180
    Presentation of work at congresses

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  • Exponential-Enhanced Characteristic of MOS Transistors and its Application to Log-Domain Circuits

     Fernandez Martinez, Daniel; Madrenas Boadas, Jordi; Dominik, Kapusta; Michalik, Piotr
    IEEE International Symposium on Circuits and Systems
    p. 2334-2337
    Presentation of work at congresses

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  • Pulse drive and capacitance measurement circuit for MEMS electrostatic actuators

     Fernandez Martinez, Daniel; Madrenas Boadas, Jordi; Dominguez Pumar, Manuel M.; Pons Nin, Joan; Ricart Campos, Jordi
    Analog integrated circuits and signal processing
    Vol. 57, num. 3, p. 225-232
    DOI: 10.1007/s10470-008-9166-9
    Date of publication: 2008-12
    Journal article

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  • A MOSFET-Based Wide-Dynamic-Range Translinear Element

     Fernandez, D; Madrenas Boadas, Jordi
    IEEE transactions on circuits and systems II: express briefs
    Vol. 55, num. 11, p. 1124-1128
    Date of publication: 2008-11
    Journal article

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  • The PERPLEXUS bio-inspired hardware platform: A flexible and modular approach

     Andres, Upegui; Thoma, Yann; Eduardo, Sanchez; Perez-Uribe, Andres; Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi; Sassatelli, Gilles
    International journal of knowledge-based intelligent engineering systems
    Vol. 12, num. 1, p. 201-212
    Date of publication: 2008-01
    Journal article

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  • An asynchronous finite state machine controller for integrated buck-boost power converters in wideband signal-tracking applications

     Fernandez Martinez, Daniel; Madrenas Boadas, Jordi; Alarcon Cot, Eduardo Jose
    IEEE International Symposium on Circuits and Systems
    p. 2210-2213
    Presentation of work at congresses

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  • On-Line Communication Mechanisms for Self-adaptative and Self-reconfigurable Systems

     Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi; Cabestany Moncusi, Joan; Katarina, Paulsson; Michael, Huebner I Juergen Becker
    Reconfigurable Communication-centric Systems-on-Chip workshop 2008 - ReCoSoC'08
    p. 93-100
    Presentation of work at congresses

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  • A Reconfigurable Translinear Cell Architecture for CMOS Field-Programmable Analog Arrays

     Fernandez Martinez, Daniel; Madrenas Boadas, Jordi; Michalik, Piotr i Dominik Kapusta
    IEEE International Conference on Electronics, Circuits and Systems
    p. 1034-1037
    Presentation of work at congresses

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  • Método de actuación resonante realimentado para actuadores electrostáticos MEMS

     Fernandez Fernandez, David; Madrenas Boadas, Jordi
    Date of request: 2008-09-18
    Invention patent

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    Método de actuación resonante realimentado para actuadores electroestáticos MEMS.

    La Invención consiste en conectar el actuador electroestático (1) a un circuito electrónico que funcione como sensor o estimador de la distancia o capacidad entre armaduras del actuador (2), obtener la velocidad a la que se mueven las armaduras mediante un derivador de dicha distancia o capacidad (3) y aplicar una señal eléctrica al actuador electroestático (4) que genere una fuerza eléctrica en el mismo sentido que la velocidad. Con esto, un actuador electroestático que inicialmente esté en la posición de reposo oscilará con cada vez mayor amplitud hasta llegar al colapso sin requerir tensiones elevadas de actuación.

  • Position, Damping and Inertia Control of Parallel-Plate Electrostatic Actuators

     Fernandez Martinez, Daniel; Madrenas Boadas, Jordi; Cosp Vilella, Jordi
    IEEE International Symposium on Circuits and Systems
    p. 2118-2121
    Presentation of work at congresses

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  • Design of a Configurable Multiprocessor for a Self-Adaptive Hardware Architecture

     Vargas, Soto J; Moreno Arostegui, Juan Manuel; Madrenas Boadas, Jordi; Cabestany Moncusi, Joan
    Conference on Design of Circuits and Integrated Systems
    p. 1-6
    Presentation of work at congresses

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  • Diccionari de Telecomunicacions

     Aguilar Igartua, Mónica; Alcober Segura, Jesus Angel; Altes Bosch, Jorge; Aragones Cervera, Xavier; Artigas Garcia, David; Bardes Llorensi, Daniel; Barlabe Dalmau, Antoni; Bragos Bardia, Ramon; Calderer Cardona, Josep; Cardama Aznar, Angel; Casademont Serra, Jordi; Casals Ibañez, Lluis; Comeron Tejero, Adolfo; Cotrina Navau, Josep; Cruz Llopis, Luis Javier de La; Dios Otin, Victor Federico; Duxans Barrobes, Helena; Esparza Martin, Oscar; Esquerra Llucià, Ignasi; Garcia Vizcaino, David; Garcies Salva, Pau; Gomez Montenegro, Carlos; Gorricho Moreno, Juan Luis; Guinjoan Gispert, Francisco; Hesselbach Serra, Xavier; Liria Righetti, Antoni; Lopez Salcedo, Jose Antonio; Madrenas Boadas, Jordi; Madueño Ruiz, María Isabel; Mestre Pons, Francesc Xavier; Monte Moreno, Enrique; Morros Rubió, Josep Ramon; Muñoz Tapia, Jose Luis; Pallares Segarra, Esteve; Pons Nin, Joan; Recolons Martos, Jaume; Rincon Rivera, David; Riu Costa, Pere Joan; Ruiz Vela, Inmaculada; Pradell Cara, Lluis; Pascual Iserte, Antonio; Prat Viñas, Luis; Rey Micolau, Francesc; Villares Piera, N. Javier
    Date of publication: 2007-03
    Book

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  • Integración Sensorial Autoadaptativa para Entornos en Red (NESSIE)

     Madrenas Boadas, Jordi; Cosp Vilella, Jordi; Calatayud Camps, Robert; Mas Raguer, Antoni; Martínez Alvarado, Luis Arturo
    Competitive project

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