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1 to 41 of 41 results
 
  • Feasibility of the embedded DRAM cells implementation with FinFET devices

     Amat Bertran, Carles; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    IEEE transactions on computers
    DOI: 10.1109/TC.2014.2375204
    Date of publication: 2014-12-05
    Journal article
  • All-digital self-adaptive PVTA variation aware clock generation system for DFS  Open access

     Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja
    European Workshop on CMOS Variability
    p. 1-4
    DOI: 10.1109/VARI.2014.6957084
    Presentation's date: 2014-09
    Presentation of work at congresses
    Access to the full text
  • SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET  Open access

     Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francesc de Borja; Vigara Campmany, Julio Enrique; Rubio Sola, Jose Antonio
    Microelectronics reliability
    Vol. 54, num. 4, p. 738-745
    DOI: 10.1016/j.microrel.2013.12.018
    Date of publication: 2014-04-01
    Journal article
  • All-digital simple clock synthesis through a glitch-free variable-length ring oscillator

     Perez Puigdemont, Jordi; Moll Echeto, Francesc de Borja; Calomarde Palomino, Antonio
    IEEE transactions on circuits and systems II: express briefs
    Vol. 61, num. 2, p. 90-94
    DOI: 10.1109/TCSII.2014.2299096
    Date of publication: 2014-02-01
    Journal article
  • Aproximación multinivel al diseño orientado a la fiabilidad de circuitos integrados analógicos y digitales

     Moll Echeto, Francesc de Borja; Aragones Cervera, Xavier; Rubio Sola, Jose Antonio; Altet Sanahujes, Josep; Reverter Cubarsí, Ferran; Calomarde Palomino, Antonio; Mateo Peña, Diego Cesar
    Competitive project
  • Variability impact on on-chip memory data paths  Open access

     Amat Bertran, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    European Workshop on CMOS Variability
    DOI: 10.1109/VARI.2014.6957086
    Presentation's date: 2014
    Presentation of work at congresses
    Access to the full text
  • Impact of finfet and III-V/Ge technology on logic and memory cell behavior

     Amat, Esteve; Calomarde Palomino, Antonio; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    IEEE transactions on device and materials reliability
    Vol. 14, num. 1, p. 1-15
    DOI: 10.1109/TDMR.2013.2291410
    Date of publication: 2013-11-20
    Journal article
  • A single event transient hardening circuit design technique based on strengthening

     Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    p. 821-824
    DOI: 10.1109/MWSCAS.2013.6674775
    Presentation's date: 2013-08-06
    Presentation of work at congresses
  • Reliability study on technology trends beyond 20nm

     Amat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    International Conference Mixed Design of Integrated Circuits and Systems
    p. 414-418
    Presentation's date: 2013-06-20
    Presentation of work at congresses
  • Novel redundant logic design for noisy low voltage scenarios

     Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; García Leyva, Lancelot
    Latin American Symposium on Circuits and Systems
    p. 1-4
    DOI: 10.1109/LASCAS.2013.6519010
    Presentation's date: 2013-02
    Presentation of work at congresses
  • MIXDES Outstanding Paper Award

     Amat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    Award or recognition
  • FinFET and III-V/Ge technology impact on 3T1D cell behavior  Open access

     Amat Bertran, Esteve; Calomarde Palomino, Antonio; Almudever, Carmen G.; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    Intel Ireland Research Conference
    Presentation's date: 2013
    Presentation of work at congresses
    Access to the full text
  • Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecture  Open access

     Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja
    Conference on Design of Circuits and Integrated Systems
    p. 539-544
    Presentation's date: 2012-11
    Presentation of work at congresses
    Access to the full text
  • PVTA tolerant self-adaptive clock generation architecture

     Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja
    International Workshop on Power and Timing Modeling, Optimization and Simulation
    p. 142-154
    DOI: 10.1007/978-3-642-36157-9_15
    Presentation's date: 2012-09
    Presentation of work at congresses
  • Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

     Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja
    IEEE International System On Chip Conference
    p. 387-392
    DOI: 10.1109/SOCC.2012.6398341
    Presentation's date: 2012-09
    Presentation of work at congresses
  • New redundant logic design concept for high noise and low voltage scenarios

     García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gomez Fernandez, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Microelectronics journal
    Vol. 42, num. 12, p. 1359-1369
    DOI: 10.1016/j.mejo.2011.09.007
    Date of publication: 2011-12
    Journal article
  • Analysis of delay mismatching of digital circuits caused by common environmental fluctuations

     Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Cotofana, Sorin
    IEEE International Symposium on Circuits and Systems
    p. 2585-2588
    DOI: 10.1109/ISCAS.2011.5938133
    Presentation's date: 2011-05-16
    Presentation of work at congresses
  • A new probabilistic design methodology of nanoscale digital circuits

     García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    International Conference on Electrical Communications and Computers
    p. 190-193
    DOI: 10.1109/CONIELECOMP.2011.5749358
    Presentation's date: 2011-02-28
    Presentation of work at congresses
  • Estimación del consumo de potencia a alto nivel de descripción. Nuevas técnicas

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    Date of publication: 2011
    Book
  • Turtle logic: Novel IC digital probabilistic design methodology  Open access

     García Leyva, Lancelot; Rubio Sola, Jose Antonio; Moll Echeto, Francesc de Borja; Calomarde Palomino, Antonio
    Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing
    p. 15-16
    Presentation's date: 2010-10-21
    Presentation of work at congresses
    Access to the full text
  • Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits  Open access

     García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    p. 1101-1104
    DOI: 10.1109/MWSCAS.2010.5548845
    Presentation's date: 2010-08-05
    Presentation of work at congresses
    Access to the full text
  • A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits  Open access

     Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    p. 141-144
    DOI: 10.1109/MWSCAS.2010.5548578
    Presentation's date: 2010-08-03
    Presentation of work at congresses
    Access to the full text
  • TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS

     Moll Echeto, Francesc de Borja; Figueras Pamies, Juan; Calomarde Palomino, Antonio; Aymerich Capdevila, Nivard; Vatajelu, Elena Ioana; Garcia Almudever, Carmen; Canal Corretger, Ramon; Pouyan, Peyman; Rubio Sola, Jose Antonio
    Competitive project
  • PRINCIPIOS DE DISEÑO Y TEST DE SISTEMAS INTEGRADOS EN TERA-ESCALA

     Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Aragones Cervera, Xavier; Amat Bertran, Esteve; Calomarde Palomino, Antonio; Mateo Peña, Diego Cesar; González, José Luis; Cotofana, Sorin; Aymerich Capdevila, Nivard; García Leyva, Lancelot; Almudever, Carmen G.; Altet Sanahujes, Josep; Landauer, Gerhard Martin; Pouyan, Peyman
    Competitive project
  • GRUP DE RECERCA DE CIRCUITS I SISTEMES INTEGRATS D'ALTES PRESTACIONS (HIPICS)

     Rubio Sola, Jose Antonio; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Gonzalez Jimenez, Jose Luis; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Molina Garcia, Marc Manel; Barajas Ojeda, Enrique; Gómez Salinas, Dídac; García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Pons Solé, Marc; Trulls Fortuny, Xavier; Dufis, Cédric Yvan; Landauer, Gerhard Martin; Garcia Almudever, Carmen; Perez Puigdemont, Jordi; Aymerich Capdevila, Nivard; Gomez Fernandez, Sergio; Aragones Cervera, Xavier
    Competitive project
  • Procedimiento para la mejora de la fiabilidad de circuitos integrados digitales en condiciones de baja relación señal a ruido

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Moll Echeto, Francesc de Borja; García Leyva, Lancelot
    Date of request: 2009-07-15
    Invention patent
  • A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs

     Andrade Miceli, Dennis Michael; Martorell, Ferran; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Microelectronics journal
    Vol. 40, num. 6, p. 952-957
    DOI: 10.1016/j.mejo.2009.01.002
    Date of publication: 2009-06
    Journal article
  • Modeling and design of reliable, process-variation aware nanoelectronic devices,circuits and systems

     Pons Solé, Marc; Altet Sanahujes, Josep; Mauricio Ferré, Juan; Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Aragones Cervera, Xavier; Mateo Peña, Diego Cesar; Rubio Sola, Jose Antonio; Gonzalez Jimenez, Jose Luis; García Leyva, Lancelot; Gómez Salinas, Dídac; Moll Echeto, Francesc de Borja
    Competitive project
  • Modeling and design of reliable, process-variation aware nanoelectronic devices,circuits and systems

     Aragones Cervera, Xavier; Mateo Peña, Diego Cesar; Pons Solé, Marc; Altet Sanahujes, Josep; Mauricio Ferré, Juan; Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Gonzalez Jimenez, Jose Luis; García Leyva, Lancelot; Gómez Salinas, Dídac; Moll Echeto, Francesc de Borja
    Competitive project
  • Design And Test Principles For Terascale Integrated Systems

     Rubio Sola, Jose Antonio; Altet Sanahujes, Josep; Aragones Cervera, Xavier; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Calomarde Palomino, Antonio; García Leyva, Lancelot; Andrade Miceli, Dennis Michael
    Competitive project
  • Nueva técnica de estimación del consumo de potencia a alto nivel de descripción

     Calomarde Palomino, Antonio
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses
  • HIGH LEVEL SPECTRAL-BASED ANALYSIS OF POWER CONSUMPTION IN DSPs SYSTEMS

     Calomarde Palomino, Antonio
    IEEE International Symposium on Circuits and Systems
    Presentation's date: 2006-05-21
    Presentation of work at congresses
  • High level spectral-based análisis of power concumption in DSP's systems

     Calomarde Palomino, Antonio; Mateo Peña, Diego Cesar; Rubio Sola, Jose Antonio
    IEEE International Symposium on Circuits and Systems
    p. 2229-2232
    DOI: 10.1109/ISCAS.2006.1693063
    Presentation's date: 2006-05
    Presentation of work at congresses
  • Transition activity estimation for digital signal processing systems

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Saludes Closa, Jordi
    Journal of low power electronics
    Vol. 1, num. 3, p. 1-9
    Date of publication: 2005-12
    Journal article
  • Analytical Estimation of Node Activity in Ripple Carry Binary Adders

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    Conference on Design of Circuits and Integrated Systems
    p. 200-205
    Presentation of work at congresses
  • Fundamentos de electrónica

     Calomarde Palomino, Antonio
    Date of publication: 2002-02-28
    Book
    Image
  • Optimizing delay time in adders for low power

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    DCIS'2002 - XVII Conference on Desing of Circuits and Integrated Systems
    p. 169-174
    Presentation of work at congresses
  • Electrónica. del dispositivo al sistema.

     Calomarde Palomino, Antonio
    Date of publication: 2000-02-28
    Book
  • A New Methodology for Design Sigma Delta Demodulator based in Low Power

     Calomarde Palomino, Antonio
    DCIS'99 - XIV Design of Circuits and Integrated Systems Conference
    Presentation's date: 1999-11-18
    Presentation of work at congresses
  • A new methodology for design sigma delta demodulator based in low power

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    DCIS'99 - XIV Design of Circuits and Integrated Systems Conference
    p. 639-644
    Presentation of work at congresses