Graphic summary
  • Show / hide key
  • Information


Scientific and technological production
  •  

1 to 33 of 33 results
  • Access to the full text
    SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET  Open access

     Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francesc de Borja; Vigara Campmany, Julio Enrique; Rubio Sola, Jose Antonio
    Microelectronics reliability
    Date of publication: 2014-04-01
    Journal article

    Read the abstract Read the abstract Access to the full text Access to the full text Open in new window  Share Reference managers Reference managers Open in new window

    In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable operation of integrated circuits. This paper presents a novel design style which reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. The independent design style of this method achieves SET mitigation and noise immunity by strengthening the sensitive nodes using a technique similar to feedback. A realization for this methodology is presented in 7 nm FinFET and in order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability as well as better noise immunity.

    In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable operation of integrated circuits. This paper presents a novel design style which reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. The independent design style of this method achieves SET mitigation and noise immunity by strengthening the sensitive nodes using a technique similar to feedback. A realization for this methodology is presented in 7 nm FinFET and in order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability as well as better noise immunity.

  • Impact of finfet and III-V/Ge technology on logic and memory cell behavior

     Amat, Esteve; Calomarde Palomino, Antonio; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    IEEE transactions on device and materials reliability
    Date of publication: 2013-11-20
    Journal article

    Read the abstract Read the abstract View View Open in new window  Share Reference managers Reference managers Open in new window

    In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios (variability and soft errors). FinFET-based circuits show the highest robustness against variability and soft error environments.

  • A single event transient hardening circuit design technique based on strengthening

     Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2013-08-06
    Presentation of work at congresses

    Read the abstract Read the abstract View View Open in new window  Share Reference managers Reference managers Open in new window

    In a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which seriously affect the system's operation. In this paper, we present a novel design strategy to reduce the impact of radiation-induced single event transients (SET) on logic circuits. This design style achieves SET mitigation by Strengthening the sensitive node using a likeness to feedback techniques. We have analyzed several techniques from hardening radiation at transistor level to a single event transient in 7nm FinFET devices. Simulation results have shown the proposed method has higher soft error robustness than the existing ones.

  • Novel redundant logic design for noisy low voltage scenarios

     Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; García Leyva, Lancelot
    Latin American Symposium on Circuits and Systems
    Presentation's date: 2013-02
    Presentation of work at congresses

    Read the abstract Read the abstract View View Open in new window  Share Reference managers Reference managers Open in new window

    The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be predominant and the reliability of the future circuits will be limited. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic and functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value. Therefore, it avoids the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs with a practical full tolerance to input with a signal to noise ratio of 5dB. Turtle Logic in accordance to Kullback Leibler Distance noise immunity measurement for a NOT gate is approximately 3.6X, 13.4X and 20.9X times better than MRF, DCVS and standard CMOS techniques, respectively, when the gates are operate, with a power supply of 0.15 volts, a temperature of 100 oC and noisy inputs with Additive White Gaussian Noise with zero mean and a standard deviation of 60mV

    The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be predominant and the reliability of the future circuits will be limited. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic and functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value. Therefore, it avoids the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs with a practical full tolerance to input with a signal to noise ratio of 5dB. Turtle Logic in accordance to Kullback Leibler Distance noise immunity measurement for a NOT gate is approximately 3.6X, 13.4X and 20.9X times better than MRF, DCVS and standard CMOS techniques, respectively, when the gates are operate, with a power supply of 0.15 volts, a temperature of 100 oC and noisy inputs with Additive White Gaussian Noise with zero mean and a standard deviation of 60mV.

  • Reliability study on technology trends beyond 20nm

     Amat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    International Conference Mixed Design of Integrated Circuits and Systems
    Presentation's date: 2013-06-20
    Presentation of work at congresses

    Read the abstract Read the abstract View View Open in new window  Share Reference managers Reference managers Open in new window

    In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits based on FinFET devices have presented the best overall behavior, since we have obtained the best performance and variability robustness. Meanwhile, the III-V/Ge-based circuits have shown the best electrical masking in front of soft errors disturbances.

    In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits based on FinFET devices have presented the best overall behavior, since we have obtained the best performance and variability robustness. Meanwhile, the III-V/Ge-based circuits have shown the best electrical masking in front of soft errors disturbances.

  • Access to the full text
    Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecture  Open access

     Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2012-11
    Presentation of work at congresses

    Access to the full text Access to the full text Open in new window  Share Reference managers Reference managers Open in new window

  • PVTA tolerant self-adaptive clock generation architecture

     Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja
    International Workshop on Power and Timing Modelling and Optimization
    Presentation's date: 2012-09
    Presentation of work at congresses

    View View Open in new window  Share Reference managers Reference managers Open in new window

  • Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

     Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja
    IEEE International System On Chip Conference
    Presentation's date: 2012-09
    Presentation of work at congresses

    View View Open in new window  Share Reference managers Reference managers Open in new window

  • New redundant logic design concept for high noise and low voltage scenarios

     García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gomez Fernandez, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Microelectronics journal
    Date of publication: 2011-12
    Journal article

    Read the abstract Read the abstract View View Open in new window  Share Reference managers Reference managers Open in new window

    This paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, where the thermal noise could be predominant and the reliability of the future circuits could be limited. The TL is a technology independent method, which aims to improve error tolerance when these errors are caused by noise within logic and functional units, sequential elements, and in general synchronous pipeline Finite State Machines. Turtle Logic operation is based on the consistency relation of redundant inputs. In the case of discrepancy, the out put of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. A two’s complement 8x8-bit pipelined Baugh–Wooley multiplier is implemented, on which several experiments reveal a perfect tolerance (0%errors) to single line discrepancies for both primary and internal nodes, with a cost of lost clock periods between 6% and 25%. The error ratio for the proposed Turtle Logic implementation with double discrepancies in both true and complementary lines are lower than 0.1% when the noise affects primary input nodes, and lower than 0.9% when the noise affects internal nodes.

  • Estimación del consumo de potencia a alto nivel de descripción. Nuevas técnicas

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    Date of publication: 2011
    Book

     Share Reference managers Reference managers Open in new window

  • Analysis of delay mismatching of digital circuits caused by common environmental fluctuations

     Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Cotofana, Sorin
    IEEE International Symposium on Circuits and Systems
    Presentation's date: 2011-05-16
    Presentation of work at congresses

    Read the abstract Read the abstract View View Open in new window  Share Reference managers Reference managers Open in new window

    Environmental conditions are changing all the time along the chip as a consequence of its own activity, provoking deviations on propagation time in digital circuits. In future technologies, the increment of devices sensitivity to environmental fluctuations yields to a wider range of possible time deviations, being for example, in an NOT gate designed in a 16nm technology 1.6 times larger than for a 45nm version. But this ratio is different for every circuit cause it depends on its fundamental structure and characteristics. In this paper the tendency of timing parameters deviations due to environmental factors fluctuation and how these deviations have deeper impact on more complex structures are analyzed. It is shown that the internal structure of the logic gates cause a mismatch between logic circuits and in future technologies it will be enlarged.

  • A new probabilistic design methodology of nanoscale digital circuits

     García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    International Conference on Electrical Communications and Computers
    Presentation's date: 2011-02-28
    Presentation of work at congresses

    Read the abstract Read the abstract View View Open in new window  Share Reference managers Reference managers Open in new window

    The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is aggravated by variations caused by the difficulties of controlling Critical Dimension (CD) in nanometer technologies. The effect of variability is the difficulty in predicting and designing circuits with precise device and circuit characteristics. In this paper, a new logic design probabilistic methodology oriented to emerging and beyond CMOS in new technologies is presented, to improve tolerance to errors due to noise, defects or manufacturability errors in single gates, logic blocks or functional units. The methodology is based on the coherence of the input redundant ports using Port Redundancy (PR) and complementary redundant ports. Simulations show an excellent performance of our approach in the presence of large random noise at the inputs.

  • TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS

     Figueras Pamies, Juan; Vatajelu, Elena Ioana; Aymerich Capdevila, Nivard; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Garcia Almudever, Carmen; Canal Corretger, Ramon; Pouyan, Peyman; Rubio Sola, Jose Antonio
    Participation in a competitive project

     Share

  • Access to the full text
    Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits  Open access

     García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2010-08-05
    Presentation of work at congresses

    Read the abstract Read the abstract Access to the full text Access to the full text Open in new window  Share Reference managers Reference managers Open in new window

    As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit reliability in the presence of faults and noise. The Turtle Logic (TL) is a new probabilistic logic method based on port redundancy and complementary data, oriented to emerging and beyond CMOS technologies. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic blocks or functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs, as well as intrinsic noise (thermal noise and flicker noise) and shot noise in the power source.

  • Access to the full text
    A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits  Open access

     Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2010-08-03
    Presentation of work at congresses

    Read the abstract Read the abstract Access to the full text Access to the full text Open in new window  Share Reference managers Reference managers Open in new window

    Abstract—Process variability and environmental fluctuations deeply affect the digital circuits performance in many different ways, one of them, the data processing time which may cause error on synchronous digital circuits due to underestimated time violations. This situation is commonly avoided adding time margins to the clock signal making it larger than nominal worstcase data process time, penalizing the global performance. In this paper a new mechanism for compensating both environmental fluctuations and process parameters variations effects on digital circuits is presented. The environmental compensation mechanism regenerates the clock signal for a pipelined system stages adding a compensated skew component depending on the local environmental conditions of every one of these stages. The process variations are corrected with a calibration circuit which adjusts the clock period in every stage taking into account its particular static deviations.

  • Access to the full text
    Turtle logic: Novel IC digital probabilistic design methodology  Open access

     García Leyva, Lancelot; Rubio Sola, Jose Antonio; Moll Echeto, Francesc de Borja; Calomarde Palomino, Antonio
    Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing
    Presentation's date: 2010-10-21
    Presentation of work at congresses

    Read the abstract Read the abstract Access to the full text Access to the full text Open in new window  Share Reference managers Reference managers Open in new window

    Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and consequently signal to noise margins are reduced, exposing computations to higher soft-error rates. In other words, the future circuits will be in a scenario where all devices may fail due to soft-error produced by trend of low SNR. In order to design reliable circuits with unreliable components, novel design techniques have been introduced. The problem of designing reliable systems with unreliable components traces back to Von Neumann, who proposed the N-tuple Modular Redundancy (NMR) technique. Additional proposals have appeared in the literature addressing the problem from the point of view of noise tolerance. For instance, the approach based on Markov Random Field theory (MRF). Take in account the Hamming distance for build basic logic gates focus to high noise and low voltage scenarios. Therefore, our proposal is based on the assumption that the devices in new and future technologies will be not perfect, noisy and hence they might fail.

  • A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs

     Andrade Miceli, Dennis Michael; Martorell, Ferran; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Microelectronics journal
    Date of publication: 2009-06
    Journal article

    View View Open in new window  Share Reference managers Reference managers Open in new window

  • Modeling and design of reliable, process-variation aware nanoelectronic devices,circuits and systems

     Aragones Cervera, Xavier; Rubio Sola, Jose Antonio; Perez Puigdemont, Jordi; Mauricio Ferré, Juan; Gómez Salinas, Dídac; García Leyva, Lancelot; Gonzalez Jimenez, Jose Luis; Pons Solé, Marc; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja
    Participation in a competitive project

     Share

  • GRUP DE RECERCA DE CIRCUITS I SISTEMES INTEGRATS D'ALTES PRESTACIONS (HIPICS)

     Rubio Sola, Jose Antonio; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Gonzalez Jimenez, Jose Luis; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Molina Garcia, Marc Manel; Barajas Ojeda, Enrique; Gómez Salinas, Dídac; García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Pons Solé, Marc; Trulls Fortuny, Xavier; Dufis, Cédric Yvan; Landauer, Gerhard Martin; Garcia Almudever, Carmen; Perez Puigdemont, Jordi; Aymerich Capdevila, Nivard; Gomez Fernandez, Sergio; Aragones Cervera, Xavier
    Participation in a competitive project

     Share

  • Design And Test Principles For Terascale Integrated Systems

     Rubio Sola, Jose Antonio; Altet Sanahujes, Josep; Aragones Cervera, Xavier; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Calomarde Palomino, Antonio; García Leyva, Lancelot; Andrade Miceli, Dennis Michael
    Participation in a competitive project

     Share

  • Modeling and design of reliable, process-variation aware nanoelectronic devices,circuits and systems

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Perez Puigdemont, Jordi; Mauricio Ferré, Juan; Gómez Salinas, Dídac; García Leyva, Lancelot; Gonzalez Jimenez, Jose Luis; Pons Solé, Marc; Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Moll Echeto, Francesc de Borja
    Participation in a competitive project

     Share

  • Procedimiento para la mejora de la fiabilidad de circuitos integrados digitales en condiciones de baja relación señal a ruido

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Moll Echeto, Francesc de Borja; García Leyva, Lancelot
    Date of request: 2009-07-15
    Invention patent

    Read the abstract Read the abstract Access to the full text Access to the full text Open in new window  Share Reference managers Reference managers Open in new window

    Procedimiento para la mejora de la fiabilidad de circuitos integrados digitales en condiciones de baja relación señal a ruido.

    Procedimiento para la mejora de la fiabilidad de circuitos integrados digitales en condiciones ambientales no favorables, o con tecnologías con dificultades de fabricación o bajo rendimiento, cuyos componentes son imperfectos.

    El procedimiento permite mejorar la fiabilidad de funcionamiento bajo condiciones adversas, tales como ruido, bajo nivel de alimentación, etc., mediante el uso de realimentación local de una serie de nodos seleccionados.

  • Nueva técnica de estimación del consumo de potencia a alto nivel de descripción

     Calomarde Palomino, Antonio
    Defense's date: 2007-03-05
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

     Share Reference managers Reference managers Open in new window

  • HIGH LEVEL SPECTRAL-BASED ANALYSIS OF POWER CONSUMPTION IN DSPs SYSTEMS

     Calomarde Palomino, Antonio
    IEEE International Symposium on Circuits and Systems
    Presentation's date: 2006-05-21
    Presentation of work at congresses

     Share Reference managers Reference managers Open in new window

  • High level spectral-based análisis of power concumption in DSP's systems

     Calomarde Palomino, Antonio; Mateo Peña, Diego Cesar; Rubio Sola, Jose Antonio; Daga Monmany, Jose Maria
    IEEE International Symposium on Circuits and Systems
    Presentation of work at congresses

     Share Reference managers Reference managers Open in new window

  • Transition activity estimation for digital signal processing systems

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Saludes Closa, Jordi
    Journal of low power electronics
    Date of publication: 2005-12
    Journal article

     Share Reference managers Reference managers Open in new window

  • Analytical Estimation of Node Activity in Ripple Carry Binary Adders

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    Conference on Design of Circuits and Integrated Systems
    Presentation of work at congresses

     Share Reference managers Reference managers Open in new window

  • Optimizing delay time in adders for low power

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    DCIS'2002 - XVII Conference on Desing of Circuits and Integrated Systems
    Presentation of work at congresses

     Share Reference managers Reference managers Open in new window

  • Fundamentos de electrónica

     Calomarde Palomino, Antonio
    Date of publication: 2002-02-28
    Book

     Share Reference managers Reference managers Open in new window

  • Electrónica. del dispositivo al sistema.

     Calomarde Palomino, Antonio
    Date of publication: 2000-02-28
    Book

     Share Reference managers Reference managers Open in new window

  • A new methodology for design sigma delta demodulator based in low power

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    DCIS'99 - XIV Design of Circuits and Integrated Systems Conference
    Presentation of work at congresses

     Share Reference managers Reference managers Open in new window

  • A New Methodology for Design Sigma Delta Demodulator based in Low Power

     Calomarde Palomino, Antonio
    DCIS'99 - XIV Design of Circuits and Integrated Systems Conference
    Presentation's date: 1999-11-18
    Presentation of work at congresses

     Share Reference managers Reference managers Open in new window