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1 to 50 of 257 results
  • Nondestructive diagnosis of mechanical misalignments in dual axis accelerometers

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Design, Test, Integration & Packaging of MEMS/MOEMS
    Presentation's date: 2013-04-18
    Presentation of work at congresses

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    Microelectromechanical systems production is still an immature technology compared to the classical semiconductor industry. MEMS fabrication and packaging processes may present misalignments which result in an improper placement of the internal microstructures or dies. In this work, the possibilities of diagnosing mechanical misalignments of dual axis IC accelerometers are explored. The used method dynamically correlates the two output signals in orthogonal directions. This leads to a Lissajous composition which is able to manifest the actual level of misalignment. The definition of a metric and its variation rate study allows the diagnosis procedure. Experimental results using a commercial dual axis capacitive accelerometer reveal diagnosis discrepancies as low as 1.1%, therefore showing the viability of the proposal.

  • BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    IEEE European Test Symposium
    Presentation of work at congresses

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    Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects

    Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects

    built-in self test integrated circuit testing three-dimensional integrated circuits

  • M-S test based on specification validation using octrees in the measure space

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    IEEE European Test Symposium
    Presentation's date: 2013-05-28
    Presentation of work at congresses

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    Testing M-S circuits is a difficult task demanding high amount of resources. To overcome these drawbacks, indirect testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure metrics. In this work, a testing technique using octrees in the measure space is presented. Octrees have been used in computer graphics with successful results for rendering, image processing and space clustering applications. In this paper are used to encode the test acceptance region with arbitrary precision after an statistical training phase. Such representation allows an efficient way to test a candidate circuit in terms of test application time. The method is applied to test a Biquad filter with encouraging results. Test escapes and test yield loss caused by parametric variations have been estimated.

  • Diagnosis of interconnect full open defects in the presence of gate leakage currents

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2013-02
    Journal article

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  • Variability-aware Architectures based on Hardware Redundancy for Nanoscale Reliable Computation

     Aymerich Capdevila, Nivard
    Defense's date: 2013-12-16
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    Durant les últimes dècades, la humanitat ha experimentat una gran millora en la qüalitat de vida gràcies a la ràpida evolució dels circuits integrats (IC). Aquesta carrera sense precedents, acompanyada d¿un gran impacte econòmic, s¿ha basat en la producció de sistemes de processat complexes a partir de components molt fiables. No obstant, la hipòtesi fonamental de components quasi-ideals, que ha estat certa en les generacions CMOS passades, sembla que avui arriba a la seva fi. De fet, a mesura que la tecnologia MOSFET es miniaturitza a nivells de nanoescala s¿apropa a limits físics fonamentals i comença a experimentar nivells més alts de variabilitat, degradació de característiques i taxes de defectes de producció. Per altra banda, circuits integrats amb un nombre de transistors cada vegada més gran requereixen una reducció en la taxa de fallades per dispositiu per tal de mantenir un nivell de fiabilitat global constant. Com a resultat, cada vegada és més important el desenvolupament d¿arquitectures de circuit capaçes de proporcioniar computació fiable i tolerar alhora nivells de variabilitat i defectes més grans.L¿objectiu principal d¿aquesta tesi és proposar i analitzar noves arquitectures tolerants a fallades basades en la redundància per a les tecnologies futures. La nostra investigació es fonamenta en els principis de la redundància establerts per von Neumann en els anys 1950 i els extén en tres noves dimensions:1. Heterogeneitat: La majoria de treballs sobre arquitectures tolerants a fallades basades en la redundància assumeixen un nivell de variabilitat homogeni en les rèpliques tal com es fa en el treball original de von Neumann. En canvi, nosaltres explorem les possibilitats de la redundància quan es té en compte la heterogeneïtat entre les rèpliques. En aquest sentit, proposem mecanismes de compensació que sel¿leccionen els pesos adequats per a maximitzar la fiabilitat global.2. Asincronia: Cadascuna de les rèpliques d¿un sistema redundant pot tenir associat un temps de processat diferent degut a la variabilitat i la degradació; especialment en les futures tecnologies. Si dissenyem el nostre sistema per a treballar de manera asíncrona localment aleshores podem considerar diferents polítiques de votació. En funció de quantes rèpliques rebem abans de prendre una decisió aleshores podem obtenir diferents balanços entre el temps de processat i la fiabilitat. Nosaltres proposem un mecanisme per proporcionar aquestes facilitats i analitzem el seu funcionament.3. Jerarquia: Finalment explorem les possibilitats de la redundància aplicada a diverses capes de jerarquia en sistemes de processat complexes. Nosaltres proposem distribuir la redundància a diversos nivells de jerarquia i analitzem els beneficis obtinguts.Especulant en l¿escenari de les futures tecnologies de circuits integrats, estenem el concepte de redundància a la màxima expressió a través de l¿estudi d¿arquitectures de nano-dispositius reals. La majoria d¿arquitectures redundants fins ara no enfronten el problema de la computació a tera-escala i les tendències de la nano-tecnologia. Des de que von Neumann va aplicar per primer cop la redundància en circuits electrònics, ningú fins ara havia tractat temes tan comuns en la nanoelectrònica com la degradació i les imperfeccions en les interconneccions des del punt de vista de la redundància. En aquesta tesi adrecem de manera àmplia la fiabilitat de sistemes de processat digitals en les properes generacions tecnològiques.

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    Built-In test of MEMS capacitive accelerometers for field failures and aging degradation.  Open access

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Design of Circuits and Integrated Systems Conference
    Presentation's date: 2012-11-28
    Presentation of work at congresses

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  • Adaptive self test of defective TSVs

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2012-11-30
    Presentation of work at congresses

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    SRAM stability metric under transient noise  Open access

     Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pamies, Juan
    Design of Circuits and Integrated Systems Conference
    Presentation's date: 2012-11-30
    Presentation of work at congresses

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    ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, temperature changes is well characterized by means of the Static Noise Margin (SNM) defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. However, a significant number of disturbance sources present a transient behavior which is ignored by the static analysis but has to be taken in consideration for a complete characterization of the cell’s behavior. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage noise is proposed based on determining the energy of the noise signal which is able to flip the cell’s state. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage noise signal able to flip the cell.

  • Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation

     Vatajelu, Elena Ioana; Figueras Pamies, Juan
    Design, Automation and Test in Europe
    Presentation's date: 2012
    Presentation of work at congresses

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  • Design of Frequency Divider with Voltage Controlled Oscillator for 60 GHz Low Power Phase-Locked Loops in 65 nm RF CMOS  Open access

     Brandano, Davide
    Defense's date: 2012-03-09
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 GHz is in today's technology a great challenge. A key reason is the inaccuracy of CMOS active and passive device models at mm-W. Three critical issues still constitute research objectives at 60 GHz in CMOS: generation of the Local Oscillator (LO) signal (1), division of the LO signal for the Phase-Locked Loop (PLL) closed loop (2) and distribution of the LO signal (3). In this Thesis, all those three critical issues are addressed and experimentally faced-up: a divide-by-2 FD for a PLL of a direct-conversion transceiver operating at mm-W frequencies in 65 nm RF CMOS technology has been designed. Critical issues such as Process, Voltage and Temperature (PVT) variations, Electromagnetic (EM) simulations and power consumption are addressed to select and design a FD with high frequency dividing range. A 60 GHz VCO is co-designed and integrated in the same die, in order to provide the FD with mm-W input signal. VCOs and FDs play critical roles in the PLL. Both of them constitute the PLL core components and they would need co-design, having a big impact in the overall performance especially because they work at the highest frequency in the PLL. Injection Locking FD (ILFD) has been chosen as the optimum FD topology to be inserted in the control loop of mm-W PLL for direct-conversion transceiver, due to the high speed requirements and the power consumption constraint. The drawback of such topology is the limited bandwidth, resulting in narrow Locking Range (LR) for WirelessHDTM applications considering the impact of PVT variations. A simulation methodology is presented in order to analyze the ILFD locking state, proposing a first divide-by-2 ILFD design with continuous tuning. In order to design a wide LR, low power consumption ILFD, the impacts of various alternatives of low/high Q tank and injection scheme are deeply analysed, since the ILFD locking range depends on the Q of the tank and injection efficiency. The proposed 3-bit dual-mixing 60 GHz divide-by-2 LC-ILFD is designed with an accumulation of switching varactors binary scaled to compensate PVT variations. It is integrated in the same die with a 4-bit 60 GHz LC-VCO. The overall circuit is designed to allow measurements of the singles blocks stand-alone and working together. The co-layout is carried on with the EM modelling process of passives devices, parasitics and transmission lines extracted from the layout. The inductors models provided by the foundry are qualified up to 40 GHz, therefore the EM analysis is a must for post-layout simulation. The PVT variations have been simulated before manufacturing and, based on the results achieved, a PLL scheme PVT robust, considering frequency calibration, has been patented. The test chip has been measured in the CEA-Leti (Grenoble) during a stay of one week. The operation principle and the optimization trade-offs among power consumption, and locking ranges of the final selected ILFD topology have been demonstrated. Even if the experimental results are not completely in agreement with the simulations, due to modelling error and inaccuracy, the proposed technique has been validated with post-measurement simulations. As demonstrated, the locking range of a low-power, discrete tuned divide-by-2 ILFD can be enhanced by increasing the injection efficiency, without the drawbacks of higher power consumption and chip area. A 4-bits wide tuning range LC-VCO for mm-W applications has been co-designed using the selected 65 nm CMOS process.

  • Layout Regularity for Design and Manufacturability  Open access

     Pons Solé, Marc
    Defense's date: 2012-10-02
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    In nowadays nanometer technology nodes, the semiconductor industry has to deal with the new challenges associated to technology scaling. On one hand, process developers face increasing manufacturing cost and variability, but also decreasing manufacturing yield. On the other hand, circuit designers and electronic design automation (EDA) developers have to reduce design turnaround time and provide the tools to cope with increasing design complexity and reduce the time-to-market. In this scenario, closer collaboration between all the actors involved is required. New approaches considering both design and manufacturing need to be explored. These are the so called design for manufacturability (DFM) techniques. A DFM trend that is becoming dominant is to make circuit layouts more regular and repetitive. The regular layout fabrics are based on the configuration of a simplied mask set, therefore reducing the manufacturing cost. Moreover, a reduced number of layout patterns is used, allowing better process variability control and optimization. Hence, regularity reduces layout complexity and therefore design complexity, allowing faster time-to-market. In this thesis, we explore forcing maximum layout regularity focusing on future technology nodes, with increasing design and manufacturability issues, where we expect layout regularity to be mandatory. With this objective, we have developed a new regular layout fabric called Via-Configurable Transistor Array (VCTA). The physical design is fully explained involving layout and geometrical considerations for transistors and interconnects. Initially, VCTA layouts developed manually have been evaluated in terms of manufacturability, but also in terms of area, energy and delay. For digital design, 32-bit binary adders designed with VCTA have been compared to standard cell layouts. For analog design, a delay-locked loop design using VCTA has been compared to its full custom version. We have also developed a physical synthesis tool that allows us to obtain VCTA circuit layouts in an automated way. Developing our own automation tool lets us controlling all the decisions made during the physical design flow to ensure that maximum layout regularity is respected. In this case the work is based on several algorithms, for instance for routing, that we have oriented to the area optimization of the layouts. Finally, in order to demonstrate the benefits of layout regularity, we have proposed a new layout regularity metric called Fixed Origin Corner Square Inspection (FOCSI). It is based on the geometrical inspection of the patterns in the layouts and it allows designers to compare regularity of designs but also how their regularity will impact their manufacturability. The FOCSI layout analysis tool can be used to optimize manufacturability.

  • Process variability in sub-16nm bulk CMOS technology

     Rubio Sola, Jose Antonio; Figueras Pamies, Juan; Vatajelu, Elena Ioana; Canal Corretger, Ramon
    Date: 2012-03-01
    Report

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  • Circuito de autotest integrado de TSVs

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date of request: 2012-10-09
    Invention patent

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    La invención presenta un sistema autotest integrado para la detección de defectos en TSVs (Through Silicon Vias o vías a través de silicio) durante la fase pre-bond, durante la cual solo uno de los terminales de la TSV es accesible. En ausencia de un defecto, el sistema evoluciona siempre hacia un mismo estado predefinido. En presencia de un defecto, el sistema evoluciona hacia otro estado diferente del establecido en ausencia de defecto. Esta invención permite a su vez que la misma estructura se utilice para la reconfiguración del circuito al final del proceso de fabricación si el resultado del test determina la presencia de una TSV defectuosa.

  • Testing IC accelerometers using Lissajous compositions

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Perspective Technologies and Methods in MEMS Design
    Presentation's date: 2011-05-11
    Presentation of work at congresses

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    Micro Electro Mechanical devices (MEMs) have widened their range of applications in a spectacular way in the last years. Reliability of MEMs devices is one of the areas that need to be improved to achieve high volume production at allowable costs. Accelerometers have in their design some mechanical and layout symmetries that can be used to improve the test and diagnosis results. In our approach we take profit of the symmetries of dual axis accelerometers to analyze and test its behavior using a procedure that composes the two orthogonal outputs when the accelerometer is spun. The complexity in the kinematics seen by the sensitive axes of the accelerometer yields rich and complex Lissajous traces that characterize the device and allows to determine the possible mismatchings in the assumed damped mass model parameters. In order to compare and quantify parameter discrepancies, a metric has been defined to allow to determine whether the DUT is within specifications or not.

  • 8T SRAM Cell with Open Defects under Voltage and Timing Variations

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Castillo Muñoz, Raul
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2011-11-16
    Presentation of work at congresses

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  • Testing dual axis IC accelerometers using Lissajous compositions

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2011-11-17
    Presentation of work at congresses

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  • Transient noise failures in SRAM cells : dynamic noise margin metric

     Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pamies, Juan
    Asian Test Symposium
    Presentation's date: 2011
    Presentation of work at congresses

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    Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM)defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise

  • New reliability mechanisms in memory design for sub-22nm technologies

     Aymerich Capdevila, Nivard; Brown, A.; Canal Corretger, Ramon; Cheng, B.; Figueras Pamies, Juan; Gonzalez Colas, Antonio Maria; Herrero Abellanas, Enric; Markov, S.; Miranda, Miguel; Pouyan, Peyman; Ramirez Garcia, Tanausu; Rubio Sola, Jose Antonio; Vatajelu, I.; Vera, Xavier; Wang, W.; Zuber, Paul; ASenov, Asen
    IEEE International On-Line Testing Symposium
    Presentation of work at congresses

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    Gate leakage impact on full open defects in interconnect lines  Open access

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram
    IEEE transactions on very large scale integration (VLSI) systems
    Date of publication: 2011-12
    Journal article

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    An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the behavior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The occurrence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are analyzed and the defective logic response of downstream gates after reaching the steady state is predicted. Experimental evidence of this behavior is presented for circuits belonging to a 180 nm and a 65 nm CMOS technologies. Technology trends show that the impact of gate leakage currents is expected to increase in future technologies.

    Postprint (author's final draft)

  • Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2011-12
    Journal article

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  • ROBUSTNESS ANALYSIS OF NANOMETRIC SRAM MEMORIES

     Vatajelu, Elena Ioana
    Defense's date: 2011-09-30
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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  • Impacto de la variabilidad en las estrategias de test y diagnóstico de circuitos micro/nanoelectrónicos

     Balado Suarez, Luz Maria; Sanahuja Moliner, Ricard; Lupon Roses, Emilio Jose; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Manich Bou, Salvador; Vatajelu, Elena Ioana; Arumi Delgado, Daniel; Figueras Pamies, Juan
    Participation in a competitive project

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    Analog circuit test based on a digital signature  Open access

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Design, Automation and Test in Europe
    Presentation's date: 2010-03-08
    Presentation of work at congresses

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    Production verification of analog circuit specifica- tions is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost on-chip parameter verification based on the analysis of a digital signature. A 65 nm CMOS on-chip monitor is proposed and validated in practice. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A digital signature is obtained using the digital code and its time duration. A metric defining a discrepancy factor is used to verify circuit parameters. The method is applied to detect possible deviations in the natural frequency of a Biquad filter. Simulated and experimental results show the possibilities of the proposal.

    Production verification of analog circuit specifica- tions is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost on-chip parameter verification based on the analysis of a digital signature. A 65 nm CMOS on-chip monitor is proposed and validated in practice. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A digital signature is obtained using the digital code and its time duration. A metric defining a discrepancy factor is used to verify circuit parameters. The method is applied to detect possible deviations in the natural frequency of a Biquad filter. Simulated and experimental results show the possibilities of the proposal.

  • Statistical analysis of SRAM parametric failure under supply voltage scaling

     Vatajelu, Elena Ioana; Figueras Pamies, Juan
    IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics
    Presentation's date: 2010-05-29
    Presentation of work at congresses

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    Postprint (author’s final draft)

  • Defective Behaviour of an 8T SRAM Cell with Open Defects

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Manich Bou, Salvador; Figueras Pamies, Juan; Di Carlo, Stefano; Prinetto, Paolo; Scionti, Alberto
    International Conference on Advances in System Testing and Validation Lifecycle
    Presentation's date: 2010-08-24
    Presentation of work at congresses

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  • Parametric Failure Analysis of Embedded SRAMs using Fast & Accurate Dynamic Analysis

     Vatajelu, Elena Ioana; Panagopoulos, Georgios; Roy, Kaushik; Figueras Pamies, Juan
    IEEE European Test Symposium
    Presentation's date: 2010-05-24
    Presentation of work at congresses

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    Postprint (author’s final draft)

  • Diagnosis of full open defects in interconnect lines with fan-out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram
    IEEE European Test Symposium
    Presentation's date: 2010-05-27
    Presentation of work at congresses

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  • Robustness of SRAM to Power Supply Noise during Leakage Power Saving in DVS

     Vatajelu, Elena Ioana; Renovell, Michel; Figueras Pamies, Juan
    International Workshop on the Impact of Low Power design on Test and Reliability(LPonTR)
    Presentation's date: 2010-05-27
    Presentation of work at congresses

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  • Identification of component deviations in analog circuits using digital signatures

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2010-11-17
    Presentation of work at congresses

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    Localization and Electrical Characterization of Interconnect Open Defects  Open access

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Beverloo, Willem; de Vries, Dirk K.; Eichenberger, Stefan; Volf, Paul A. J.
    IEEE transactions on semiconductor manufacturing
    Date of publication: 2010-02
    Journal article

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    A technique for extracting the electrical and topological parameters of open defects in process monitor lines is presented. The procedure is based on frequency-domain measurements performed at both end points of the line. The location as well as the resistive value of the open defect are derived from attenuation and phase shift measurements. The characteristic defect-free impedance of the line and its propagation constant are considered to be unknowns, and their values are also derived from the above measurements. In this way, the impact of process parameter variations on the proposed model is diminished. The experimental setup required to perform the characterization measurements and a simple graphical procedure to determine the defect and line parameters are presented. Experimental results show a good agreement between the predicted location of the open and its real location, found by optical beam induced resistance change inspection. Errors smaller than 2% of the total length of the line have been observed in the experiments.

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    Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals  Open access

     Champac Vilela, Victor Hugo; Avendaño, Victor; Figueras Pamies, Juan
    IEEE transactions on very large scale integration (VLSI) systems
    Date of publication: 2010-02
    Journal article

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    Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.

  • TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS

     Figueras Pamies, Juan; Calomarde Palomino, Antonio; Aymerich Capdevila, Nivard; Moll Echeto, Francesc de Borja; Vatajelu, Elena Ioana; Garcia Almudever, Carmen; Canal Corretger, Ramon; Pouyan, Peyman; Rubio Sola, Jose Antonio
    Participation in a competitive project

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  • Detectability study of single via opens in a 90nm technology design

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-10
    Report

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  • Diagnosis of full open defects in interconnect lines with fan-out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-11
    Report

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  • Simulations of interconnect open faults

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-11
    Report

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  • Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures

     Balado Suarez, Luz Maria; Lupon Roses, Emilio Jose; Figueras Pamies, Juan
    IEEE transactions on circuits and systems I: regular papers
    Date of publication: 2009-04
    Journal article

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  • Models for Bridging Defects

     Renovell, Michel; Azais, Florence; Figueras Pamies, Juan; Rodríguez Montañés, Rosa; Arumi Delgado, Daniel
    Date of publication: 2009-11-01
    Book chapter

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  • Open defects in nanometer technologies

     Figueras Pamies, Juan; Rodríguez Montañés, Rosa; Arumi Delgado, Daniel
    Date of publication: 2009-11-01
    Book chapter

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  • NUEVAS ESTRATEGIAS DE DIAGNÓSTICO Y TEST PARA CIRCUITOS INTEGRADOS CMOS NANOMÉTRICOS

     Balado Suarez, Luz Maria; Sanahuja Moliner, Ricard; Barcons Xixons, Victor; Ferre Fabregas, Antoni; Figueras Pamies, Juan
    Participation in a competitive project

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  • Digital signature generator for mixed-signal testing

     Sanahuja Moliner, Ricard; Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    IEEE European Test Symposium
    Presentation's date: 2009-05-26
    Presentation of work at congresses

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  • Experimental Characterization of CMOS Interconnect Open Defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2008-01
    Journal article

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  • Data Dependence of Delay Distribution for a Planar Bus

     Moll Echeto, Francesc de Borja; Figueras Pamies, Juan; Rubio Sola, Jose Antonio
    18th International Workshop, PATMOS 2008
    Presentation's date: 2008-09-10
    Presentation of work at congresses

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  • Impact of Gate Leakage Currents on Full Open Defects in SRAM Cells

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2008-11-12
    Presentation of work at congresses

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  • X-Y Zoning Circuit for Low-Cost Signal Monitoring

     Balado Suarez, Luz Maria; Sanahuja Moliner, Ricard; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation of work at congresses

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  • Time-dependent behaviour of full open defects in interconnecting lines

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C; Kruseman, Bram
    INTERNATIONAL TEST CONFERENCE
    Presentation's date: 2008-10-29
    Presentation of work at congresses

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  • VTS07 Best Paper Award

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Rodríguez-Montañés, R; Eichenberger, Stefan; Hora, C; Kruseman, Bram; Lousberg, M; Majhi, A K
    Award or recognition

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  • Full open defects under tunnelling leakage current in nanometric CMOS

     Arumi Delgado, Daniel; Rodríguez-Montañés, R; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C; Kruseman, Bram
    IEEE VLSI Test Symposium
    Presentation's date: 2008-04-28
    Presentation of work at congresses

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  • The Impact of Supply Voltage Reduction on The Static Noise Margins of 6 T-Sram Cell

     Vatajelu, Elena Ioana; Figueras Pamies, Juan
    Control engineering and applied informatics
    Date of publication: 2008-12
    Journal article

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  • IDDQ-based diagnosis at very low voltage (VLV) for bridging defects

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram; Lousberg, M.
    Electronics Letters
    Date of publication: 2007-03
    Journal article

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  • Access to the full text
    Impact of gate tunnelling leakage on CMOS circuits with full open defects  Open access  awarded activity

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Eichenberger, S.; Hora, Camelia; Kruseman, B.
    Electronics Letters
    Date of publication: 2007-10
    Journal article

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    Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.

    Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.

    Electronics Letter of the Month