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1 to 50 of 269 results
  • Electrical localisation of full open defects in comb-meander-comb structures

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Electronics Letters
    Vol. 50, num. 23, p. 1682-1683
    DOI: 10.1049/el.2014.3104
    Date of publication: 2014-11-06
    Journal article

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    Test structures are key elements to characterise and identify the main contributors to yield loss in wiring structures. Among such monitors, comb-meander-comb structures have been widely used owing to their simplicity and reduced number of pads. With continuous scaling of dimensions and use of copper in interconnections, open defects has arisen as the most common defect affecting the interconnection, focusing thus on an important part of the research effort. In fact, present electrical methodologies are able to detect, localise and predict the resistance of weak (resistive) opens. However, such methodologies are not able to locate full opens. This lack of information may be useful for faster ramp-up and yield improvement, among others. In this context, a simple electrical methodology to predict the location of full opens in comb-meander-comb structures is presented. Experimental measurements carried out in a 65 nm technology die corroborate the feasibility of the approach.

  • Pre-bond testing of weak defects in TSVs

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    IEEE International On-Line Testing Symposium
    p. 31-36
    DOI: 10.1109/IOLTS.2014.6873668
    Presentation's date: 2014-07-07
    Presentation of work at congresses

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    Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and may undergo defects during the fabrication process and also during their life time. The detection of defective TSVs in the earliest process step is of major concern. For this reason, testing TSVs is usually done at different stages of the fabrication process. In fact, effective pre-bond testing is a key factor to prevent stacking yield loss. Extensive research effort has been devoted to develop efficient pre-bond techniques. In this direction, two main approaches have been explored: pre-bond probing and built-in self test (BIST) techniques. Pre-bond probing is challenging since TSVs are too small for standard test probes and the number of probe pads for testing is not affordable. Present BIST proposals have some disadvantages depending on the particular solution considered, namely: the detection of certain types of defects solely, inability to detect weak defects, large area overhead and long test application time. In this context, this work proposes a simple solution, adding low area overhead and fast application test procedure. Simulation results confirm the proposal viability. © 2014 IEEE.

  • Post-Bond test of through-silicon vias with open defects

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan
    IEEE European Test Symposium
    p. 1-6
    DOI: 10.1109/ETS.2014.6847816
    Presentation's date: 2014-05-29
    Presentation of work at congresses

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    Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent failure mechanism affecting TSVs. Although there is considerable research effort dedicated to improve TSVs testing, no much attention has been paid to weak defects, especially to weak open defects (resistive opens) causing small delays. In this work, a testing strategy is proposed to detect small delay defects by means of a post-bond oscillation test. Variations in the Duty Cycle of transmitted signals after unbalanced logic gates are shown to detect weak open defects in TSVs. HSPICE simulations including process parameter variations show the effectiveness of the method in the detection of weak open defects above 1 kO.

  • Diagnosis of parametric defects in dual axis IC accelerometers

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Microsystem technologies-Micro-and nanosystems-Information storage and processing
    DOI: 10.1007/s00542-014-2218-4
    Date of publication: 2014-05-22
    Journal article

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    Test of dual axis accelerometers based on specifications compliance  Open access

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2013-11-28
    Presentation of work at congresses

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  • M-S test based on specification validation using octrees in the measure space

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    IEEE European Test Symposium
    p. 70-75
    DOI: 10.1109/ETS.2013.6569359
    Presentation's date: 2013-05-28
    Presentation of work at congresses

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    Testing M-S circuits is a difficult task demanding high amount of resources. To overcome these drawbacks, indirect testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure metrics. In this work, a testing technique using octrees in the measure space is presented. Octrees have been used in computer graphics with successful results for rendering, image processing and space clustering applications. In this paper are used to encode the test acceptance region with arbitrary precision after an statistical training phase. Such representation allows an efficient way to test a candidate circuit in terms of test application time. The method is applied to test a Biquad filter with encouraging results. Test escapes and test yield loss caused by parametric variations have been estimated.

  • Nondestructive diagnosis of mechanical misalignments in dual axis accelerometers

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Design, Test, Integration & Packaging of MEMS/MOEMS
    Presentation's date: 2013-04-18
    Presentation of work at congresses

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    Microelectromechanical systems production is still an immature technology compared to the classical semiconductor industry. MEMS fabrication and packaging processes may present misalignments which result in an improper placement of the internal microstructures or dies. In this work, the possibilities of diagnosing mechanical misalignments of dual axis IC accelerometers are explored. The used method dynamically correlates the two output signals in orthogonal directions. This leads to a Lissajous composition which is able to manifest the actual level of misalignment. The definition of a metric and its variation rate study allows the diagnosis procedure. Experimental results using a commercial dual axis capacitive accelerometer reveal diagnosis discrepancies as low as 1.1%, therefore showing the viability of the proposal.

  • Diagnosis of interconnect full open defects in the presence of gate leakage currents

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram
    IEEE transactions on computer-aided design of integrated circuits and systems
    Vol. 32, num. 2, p. 301-312
    DOI: 10.1109/TCAD.2012.2228269
    Date of publication: 2013-02
    Journal article

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  • BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    IEEE European Test Symposium
    DOI: 10.1109/ETS.2013.6569389
    Presentation of work at congresses

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    Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects

    built-in self test integrated circuit testing three-dimensional integrated circuits

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    SRAM stability metric under transient noise  Open access

     Gómez Pau, Álvaro; Renovell, Michel; Figueras Pamies, Juan
    Design of Circuits and Integrated Systems Conference
    Presentation's date: 2012-11-30
    Presentation of work at congresses

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    ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, temperature changes is well characterized by means of the Static Noise Margin (SNM) defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. However, a significant number of disturbance sources present a transient behavior which is ignored by the static analysis but has to be taken in consideration for a complete characterization of the cell’s behavior. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage noise is proposed based on determining the energy of the noise signal which is able to flip the cell’s state. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage noise signal able to flip the cell.

  • Adaptive self test of defective TSVs

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2012-11-30
    Presentation of work at congresses

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    Built-In test of MEMS capacitive accelerometers for field failures and aging degradation.  Open access

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Design of Circuits and Integrated Systems Conference
    p. 223-228
    Presentation's date: 2012-11-28
    Presentation of work at congresses

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  • Circuito de autotest integrado de TSVs

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date of request: 2012-10-09
    Invention patent

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    La invención presenta un sistema autotest integrado para la detección de defectos en TSVs (Through Silicon Vias o vías a través de silicio) durante la fase pre-bond, durante la cual solo uno de los terminales de la TSV es accesible. En ausencia de un defecto, el sistema evoluciona siempre hacia un mismo estado predefinido. En presencia de un defecto, el sistema evoluciona hacia otro estado diferente del establecido en ausencia de defecto. Esta invención permite a su vez que la misma estructura se utilice para la reconfiguración del circuito al final del proceso de fabricación si el resultado del test determina la presencia de una TSV defectuosa.

  • Process variability in sub-16nm bulk CMOS technology

     Rubio Sola, Jose Antonio; Figueras Pamies, Juan; Vatajelu, Elena Ioana; Canal Corretger, Ramon
    Date: 2012-03-01
    Report

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  • Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation

     Figueras Pamies, Juan; Vatajelu, Elena Iona
    Design, Automation and Test in Europe
    p. 1343-1348
    Presentation's date: 2012
    Presentation of work at congresses

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    Gate leakage impact on full open defects in interconnect lines  Open access

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram
    IEEE transactions on very large scale integration (VLSI) systems
    Vol. 19, num. 12, p. 2209-2220
    DOI: 10.1109/TVLSI.2010.2077315
    Date of publication: 2011-12
    Journal article

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    An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the behavior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The occurrence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are analyzed and the defective logic response of downstream gates after reaching the steady state is predicted. Experimental evidence of this behavior is presented for circuits belonging to a 180 nm and a 65 nm CMOS technologies. Technology trends show that the impact of gate leakage currents is expected to increase in future technologies.

    Postprint (author's final draft)

  • Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram
    IEEE transactions on computer-aided design of integrated circuits and systems
    Vol. 30, num. 12, p. 1911-1922
    DOI: 10.1109/TCAD.2011.2165071
    Date of publication: 2011-12
    Journal article

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  • Testing dual axis IC accelerometers using Lissajous compositions

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    p. 1-4
    Presentation's date: 2011-11-17
    Presentation of work at congresses

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  • 8T SRAM Cell with Open Defects under Voltage and Timing Variations

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Castillo Muñoz, Raul
    Conference on Design of Circuits and Integrated Systems
    p. 155-160
    Presentation's date: 2011-11-16
    Presentation of work at congresses

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  • ROBUSTNESS ANALYSIS OF NANOMETRIC SRAM MEMORIES

     Vatajelu, Elena Ioana
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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  • Testing IC accelerometers using Lissajous compositions

     Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Perspective Technologies and Methods in MEMS Design
    p. 75-81
    Presentation's date: 2011-05-11
    Presentation of work at congresses

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    Micro Electro Mechanical devices (MEMs) have widened their range of applications in a spectacular way in the last years. Reliability of MEMs devices is one of the areas that need to be improved to achieve high volume production at allowable costs. Accelerometers have in their design some mechanical and layout symmetries that can be used to improve the test and diagnosis results. In our approach we take profit of the symmetries of dual axis accelerometers to analyze and test its behavior using a procedure that composes the two orthogonal outputs when the accelerometer is spun. The complexity in the kinematics seen by the sensitive axes of the accelerometer yields rich and complex Lissajous traces that characterize the device and allows to determine the possible mismatchings in the assumed damped mass model parameters. In order to compare and quantify parameter discrepancies, a metric has been defined to allow to determine whether the DUT is within specifications or not.

  • Transient noise failures in SRAM cells : dynamic noise margin metric

     Gómez Pau, Álvaro; Renovell, Michel; Figueras Pamies, Juan; Vatajelu, Elena Iona
    Asian Test Symposium
    p. 413-418
    DOI: 10.1109/ATS.2011.64
    Presentation's date: 2011
    Presentation of work at congresses

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    Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM)defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise

  • New reliability mechanisms in memory design for sub-22nm technologies

     Aymerich Capdevila, Nivard; Brown, A.; Canal Corretger, Ramon; Cheng, B.; Figueras Pamies, Juan; Gonzalez Colas, Antonio Maria; Herrero Abellanas, Enric; Markov, S.; Miranda, Miguel; Pouyan, Peyman; Ramirez Garcia, Tanausu; Rubio Sola, Jose Antonio; Vatajelu, I.; Vera, Xavier; Wang, W.; Zuber, Paul; ASenov, Asen
    IEEE International On-Line Testing Symposium
    p. 111-114
    DOI: 10.1109/IOLTS.2011.5993820
    Presentation of work at congresses

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  • Identification of component deviations in analog circuits using digital signatures

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    p. 187-192
    Presentation's date: 2010-11-17
    Presentation of work at congresses

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  • Diagnosis of full open defects in interconnect lines with fan-out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-11
    Report

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  • Simulations of interconnect open faults

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-11
    Report

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  • Detectability study of single via opens in a 90nm technology design

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Date: 2010-10
    Report

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  • Defective Behaviour of an 8T SRAM Cell with Open Defects

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Manich Bou, Salvador; Figueras Pamies, Juan; Di Carlo, Stefano; Prinetto, Paolo; Scionti, Alberto
    International Conference on Advances in System Testing and Validation Lifecycle
    p. 81-86
    DOI: 10.1109/VALID.2010.19
    Presentation's date: 2010-08-24
    Presentation of work at congresses

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  • Statistical analysis of SRAM parametric failure under supply voltage scaling

     Vatajelu, Elena Ioana; Figueras Pamies, Juan
    IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics
    p. 1-6
    DOI: 10.1109/AQTR.2010.5520825
    Presentation's date: 2010-05-29
    Presentation of work at congresses

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    Postprint (author’s final draft)

  • Diagnosis of full open defects in interconnect lines with fan-out

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram
    IEEE European Test Symposium
    p. 233-238
    Presentation's date: 2010-05-27
    Presentation of work at congresses

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  • Robustness of SRAM to Power Supply Noise during Leakage Power Saving in DVS

     Vatajelu, Elena Ioana; Renovell, Michel; Figueras Pamies, Juan
    International Workshop on the Impact of Low Power design on Test and Reliability(LPonTR)
    p. 1-3
    Presentation's date: 2010-05-27
    Presentation of work at congresses

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  • Parametric Failure Analysis of Embedded SRAMs using Fast & Accurate Dynamic Analysis

     Vatajelu, Elena Ioana; Panagopoulos, Georgios; Roy, Kaushik; Figueras Pamies, Juan
    IEEE European Test Symposium
    p. 69-74
    Presentation's date: 2010-05-24
    Presentation of work at congresses

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    Postprint (author’s final draft)

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    Analog circuit test based on a digital signature  Open access

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Design, Automation and Test in Europe
    p. 1641-1644
    Presentation's date: 2010-03-08
    Presentation of work at congresses

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    Production verification of analog circuit specifica- tions is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost on-chip parameter verification based on the analysis of a digital signature. A 65 nm CMOS on-chip monitor is proposed and validated in practice. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A digital signature is obtained using the digital code and its time duration. A metric defining a discrepancy factor is used to verify circuit parameters. The method is applied to detect possible deviations in the natural frequency of a Biquad filter. Simulated and experimental results show the possibilities of the proposal.

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    Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals  Open access

     Champac Vilela, Victor Hugo; Avendaño, Victor; Figueras Pamies, Juan
    IEEE transactions on very large scale integration (VLSI) systems
    Vol. 18, num. 2, p. 256-269
    DOI: 10.1109/TVLSI.2008.2010398
    Date of publication: 2010-02
    Journal article

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    Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.

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    Localization and Electrical Characterization of Interconnect Open Defects  Open access

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Beverloo, Willem; de Vries, Dirk K.; Eichenberger, Stefan; Volf, Paul A. J.
    IEEE transactions on semiconductor manufacturing
    Vol. 23, num. 1, p. 65-76
    DOI: 10.1109/TSM.2009.2039187
    Date of publication: 2010-02
    Journal article

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    A technique for extracting the electrical and topological parameters of open defects in process monitor lines is presented. The procedure is based on frequency-domain measurements performed at both end points of the line. The location as well as the resistive value of the open defect are derived from attenuation and phase shift measurements. The characteristic defect-free impedance of the line and its propagation constant are considered to be unknowns, and their values are also derived from the above measurements. In this way, the impact of process parameter variations on the proposed model is diminished. The experimental setup required to perform the characterization measurements and a simple graphical procedure to determine the defect and line parameters are presented. Experimental results show a good agreement between the predicted location of the open and its real location, found by optical beam induced resistance change inspection. Errors smaller than 2% of the total length of the line have been observed in the experiments.

  • TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS

     Moll Echeto, Francesc de Borja; Figueras Pamies, Juan; Calomarde Palomino, Antonio; Aymerich Capdevila, Nivard; Vatajelu, Elena Ioana; Garcia Almudever, Carmen; Canal Corretger, Ramon; Pouyan, Peyman; Rubio Sola, Jose Antonio
    Competitive project

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    Verifying analog circuits based on a digital signature  Open access

     Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    p. 1-6
    Presentation's date: 2009-11-18
    Presentation of work at congresses

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    Veri¿cation of analog circuit speci¿cations is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost parameter veri¿cation based on statistical analysis of a digital signature. A CMOS on-chip monitor and sampler circuit generates the digital signature of the CUT. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A metric to be used to discriminate the golden and defective signatures is also proposed. The metric is based on the de¿nition of a discrepancy factor performing circuit parameter identi¿cation via statistical and pre-training procedures. The proposed method is applied to verify possible deviations on the natural frequency of a Biquad ¿lter. Simulation results show the possibilities of the proposal.

    Verification of analog circuit specifications is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost parameter verification based on statistical analysis of a digital signature. A CMOS on-chip monitor and sampler circuit generates the digital signature of the CUT. The monitor composes two signals (x(t); y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x; y) location. A metric to be used to discriminate the golden and defective signatures is also proposed. The metric is based on the definition of a discrepancy factor performing circuit parameter identification via statistical and pre-training procedures. The proposed method is applied to verify possible deviations on the natural frequency of a Biquad filter. Simulation results show the possibilities of the proposal.

  • Diagnosis of Full Open Defects in Interconnect Lines with Large Fan-out

     Arumi Delgado, Daniel; Rodríguez-Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2009-11-18
    Presentation of work at congresses

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  • Open defects in nanometer technologies

     Figueras Pamies, Juan; Rodríguez Montañés, Rosa; Arumi Delgado, Daniel
    DOI: 10.1007/978-90-481-3282-9
    Date of publication: 2009-11-01
    Book chapter

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  • Models for Bridging Defects

     Renovell, Michel; Azais, Florence; Figueras Pamies, Juan; Rodríguez Montañés, Rosa; Arumi Delgado, Daniel
    DOI: 10.1007/978-90-481-3282-9
    Date of publication: 2009-11-01
    Book chapter

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  • Digital signature generator for mixed-signal testing

     Sanahuja Moliner, Ricard; Gómez Pau, Álvaro; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    IEEE European Test Symposium
    Presentation's date: 2009-05-26
    Presentation of work at congresses

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  • Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures

     Balado Suarez, Luz Maria; Lupon Roses, Emilio Jose; Figueras Pamies, Juan
    IEEE transactions on circuits and systems I: regular papers
    Vol. 56, num. 4, p. 754-762
    DOI: 10.1109/TCSI.2008.2004342
    Date of publication: 2009-04
    Journal article

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  • NUEVAS ESTRATEGIAS DE DIAGNÓSTICO Y TEST PARA CIRCUITOS INTEGRADOS CMOS NANOMÉTRICOS

     Balado Suarez, Luz Maria; Sanahuja Moliner, Ricard; Barcons Xixons, Victor; Ferre Fabregas, Antoni; Figueras Pamies, Juan
    Competitive project

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  • Qualitat en Electrònica: Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades

     Figueras Pamies, Juan; Carrasco Lopez, Juan Antonio; Lupon Roses, Emilio Jose; Manich Bou, Salvador; Rodríguez Montañés, Rosa; Rius Vazquez, Jose; Balado Suarez, Luz Maria; Ferre Fabregas, Antoni; Suñe Socias, Victor Manuel; Arumi Delgado, Daniel; Sanahuja Moliner, Ricard
    Competitive project

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  • HI2008-0041 Acción integrada de investigación científica y tecnológica entre España e Italia

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Manich Bou, Salvador
    Competitive project

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  • The Impact of Supply Voltage Reduction on The Static Noise Margins of 6 T-Sram Cell

     Vatajelu, Elena Ioana; Figueras Pamies, Juan
    Control engineering and applied informatics
    Vol. 10, num. 4, p. 49-62
    Date of publication: 2008-12
    Journal article

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  • Impact of Gate Leakage Currents on Full Open Defects in SRAM Cells

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2008-11-12
    Presentation of work at congresses

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  • Time-dependent behaviour of full open defects in interconnecting lines

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pamies, Juan; Eichenberger, Stefan; Hora, C; Kruseman, Bram
    INTERNATIONAL TEST CONFERENCE
    p. 1-10
    Presentation's date: 2008-10-29
    Presentation of work at congresses

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  • Data Dependence of Delay Distribution for a Planar Bus

     Moll Echeto, Francesc de Borja; Figueras Pamies, Juan; Rubio Sola, Jose Antonio
    18th International Workshop, PATMOS 2008
    p. 409-418
    Presentation's date: 2008-09-10
    Presentation of work at congresses

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  • VTS07 Best Paper Award

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Rodríguez-Montañés, R; Eichenberger, Stefan; Hora, C; Kruseman, Bram; Lousberg, M; Majhi, A K
    Award or recognition

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