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  • Exploiting reuse locality on inclusive shared last-level caches

     Albericio, Jorge; Ibáñez Marín, Pablo Enrique; Viñals Yufera, Víctor; Llaberia Griño, Jose M.
    ACM transactions on architecture and code optimization
    Date of publication: 2013-01
    Journal article

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  • ABS: a low-cost adaptive controller for prefetching in a banked shared last-level cache

     Albericio, Jorge; Gran, Rubén; Ibañez, Pablo; Viñals Yúfera, Víctor; Llaberia Griño, Jose M.
    ACM transactions on architecture and code optimization
    Date of publication: 2012-01
    Journal article

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  • Effcient handling of lock hand-off in DSM multiprocessors with buffering coherence controllers

     Sahelices, Benjamin; de Dios, Agustín; Ibañez, Pablo; Viñals Yufera, Victor; Llaberia Griño, Jose M.
    Journal of computer science and technology
    Date of publication: 2012-01
    Journal article

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  • Mitosis Based Speculative Multithreaded Architectures  Open access

     Madriles Gimeno, Carlos
    Defense's date: 2012-07-23
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    In the last decade, industry made a right-hand turn and shifted towards multi-core processor designs, also known as Chip-Multi-Processors (CMPs), in order to provide further performance improvements under a reasonable power budget, design complexity, and validation cost. Over the years, several processor vendors have come out with multi-core chips in their product lines and they have become mainstream, with the number of cores increasing in each processor generation. Multi-core processors improve the performance of applications by exploiting Thread Level Parallelism (TLP) while the Instruction Level Parallelism (ILP) exploited by each individual core is limited. These architectures are very efficient when multiple threads are available for execution. However, single-thread sections of code (single-thread applications and serial sections of parallel applications) pose important constraints on the benefits achieved by parallel execution, as pointed out by Amdahl’s law. Parallel programming, even with the help of recently proposed techniques like transactional memory, has proven to be a very challenging task. On the other hand, automatically partitioning applications into threads may be a straightforward task in regular applications, but becomes much harder for irregular programs, where compilers usually fail to discover sufficient TLP. In this scenario, two main directions have been followed in the research community to take benefit of multi-core platforms: Speculative Multithreading (SpMT) and Non-Speculative Clustered architectures. The former splits a sequential application into speculative threads, while the later partitions the instructions among the cores based on data-dependences but avoid large degree of speculation. Despite the large amount of research on both these approaches, the proposed techniques so far have shown marginal performance improvements. In this thesis we propose novel schemes to speed-up sequential or lightly threaded applications in multi-core processors that effectively address the main unresolved challenges of previous approaches. In particular, we propose a SpMT architecture, called Mitosis, that leverages a powerful software value prediction technique to manage inter-thread dependences, based on pre-computation slices (p-slices). Thanks to the accuracy and low cost of this technique, Mitosis is able to effectively parallelize applications even in the presence of frequent dependences among threads. We also propose a novel architecture, called Anaphase, that combines the best of SpMT schemes and clustered architectures. Anaphase effectively exploits ILP, TLP and Memory Level Parallelism (MLP), thanks to its unique finegrain thread decomposition algorithm that adapts to the available parallelism in the application.

  • Vectorized register tiling

     Berna Juan, Alejandro; Jimenez Castells, Marta; Llaberia Griño, Jose M.
    Date: 2012-01
    Report

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  • Source code transformations for efficient SIMD code generation

     Berna Juan, Alejandro; Jimenez Castells, Marta; Llaberia Griño, Jose M.
    Date: 2012-01
    Report

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    Source-to-Source transformations for efficient SIMD code generation  Open access

     Berna Juan, Alejandro; Jimenez Castells, Marta; Llaberia Griño, Jose M.
    Jornadas de Paralelismo
    Presentation's date: 2011-09
    Presentation of work at congresses

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    In the last years, there has been much effort in commercial compilers to generate efficient SIMD instructions-based code sequences from conventional sequential programs. However, the small numbers of compilers that can automatically use these instructions achieve in most cases unsatisfactory results. Therefore, the code often has to be written manually in assembly language or using compiler built-in functions to achieve high performance. In this work, we present source-to-source transformations that help commercial vectorizing compilers to generate efficient SIMD code. Experimental results show that excellent performance can be achieved. In particular, for the problem of matrix product (SGEMM) we almost achieve as high performance as hand-optimized numerical libraries. Our source-tosource transformations are based on the scalar replacement and unroll and jam transformations presented by Callahan et all. In particular, we extend the use of scalar replacement to vectorial replacement and combine this transformation with unroll and jam and outer loop vectorization to fully exploit the vector register level and thus to help the compiler to generate efficient SIMD code. We will show experimentally the effectiveness of our proposal.

  • Managing Dynamic Non-Uniform Cache Architectures  Open access

     Lira Rueda, Javier
    Defense's date: 2011-11-25
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    Researchers from both academia and industry agree that future CMPs will accommodate large shared on-chip last-level caches. However, the exponential increase in multicore processor cache sizes accompanied by growing on-chip wire delays make it difficult to implement traditional caches with a single, uniform access latency. Non-Uniform Cache Access (NUCA) designs have been proposed to address this situation. A NUCA cache divides the whole cache memory into smaller banks that are distributed along the chip and can be accessed independently. Response time in NUCA caches does not only depend on the latency of the actual bank, but also on the time required to reach the bank that has the requested data and to send it to the core. So, the NUCA cache allows those banks that are located next to the cores to have lower access latencies than the banks that are further away, thus mitigating the effects of the cache’s internal wires. These cache architectures have been traditionally classified based on their placement decisions as static (S-NUCA) or dynamic (DNUCA). In this thesis, we have focused on D-NUCA as it exploits the dynamic features that NUCA caches offer, like data migration. The flexibility that D-NUCA provides, however, raises new challenges that hardens the management of this kind of cache architectures in CMP systems. We have identified these new challenges and tackled them from the point of view of the four NUCA policies: replacement, access, placement and migration. First, we focus on the challenges introduced by the replacement policy in D-NUCA. Data migration makes most frequently accessed data blocks to be concentrated on the banks that are closer to the processors. This creates big differences in the average usage rate of the NUCA banks, being the banks that are close to the processors the most accessed banks, while the banks that are further away are not accessed so often. Upon a replacement in a particular bank of the NUCA cache, the probabilities of the evicted data block to be reused by the program will differ if its last location in the NUCA cache was a bank that are close to the processors, or not. The decentralized nature of NUCA, however, prevents a NUCA bank from knowing that other bank is constantly evicting data blocks that are later being reused. We propose three different techniques to dealwith the replacement policy, being The Auction the most successful one. Then, we deal with the challenges in the access policy. As data blocks can be mapped in multiple banks within the NUCA cache. Finding the requesting data in a D-NUCA cache is a difficult task. In addition, data can freely move between these banks, thus the search scheme must look up all banks where the requesting data block can be mapped to ascertain if it is in the NUCA cache, or not. We have proposed HK-NUCA. This is a search scheme that uses home knowledge to effectively reduce the average number of messages introduced to the on-chip network to satisfy a memory request. With regard to the placement policy, this thesis shows the implementation of a hybrid NUCA cache. We have proposed a novel placement policy that accomodates both memory technologies, SRAM and eDRAM, in a single NUCA cache. Finally, in order to deal with the migration policy in D-NUCA caches, we propose The Migration Prefetcher. This is a technique that anticipates data migrations. Summarizing, in this thesis we propose different techniques to efficiently manage future D-NUCA cache architectures on CMPs. We demonstrate the effectivity of our techniques to deal with the challenges introduced by D-NUCA caches. Our techniques outperform existing solutions in the literature, and are in most cases more energy efficient.

    CMPs actuales integran memorias cache de último nivel cada vez más grandes dentro del chip. Roadmaps en la industria y trabajos en ámbito académico muestran que esta tendencia seguirá en los próximos años. Sin embargo, los altos retrasos en la red de interconexión y el cableado hace que sea cada vez más difícil de implementar memorias cachés tradicionales con una única y uniforme latencia de acceso. Para solventar esta situación aparecieron los diseños NUCA (Non-Uniform Cache Access). Una caché de tipo NUCA divide una memoria grande en bloques más pequeños que se distribuyen a lo largo del chip y pueden ser accedidos de manera independiente. De esta manera el tiempo de respuesta en una caché NUCA no depende sólo de la latencia de un banco, sino que también se tiene en cuenta el tiempo de enrutamiento de la petición hasta y desde el banco de la NUCA que responde. La posición física de un banco en el chip es clave para determinar la latencia de acceso a NUCA, entonces bancos que se encuentren más cerca de los cores tendrán menores latencias de acceso que otros que estén más alejados. Las cachés NUCA se pueden clasificar como estáticas (S-NUCA) o dinámicas (D-NUCA), basándonos en sus decisiones de emplazamiento. Esta tesis se centra en D-NUCA. Este diseño permite a un dato migrar de banco en banco a fín de reducir la latencia de futuros accesos a ese dato, pero también ofrece otros retos que deben ser investigados para gestionar estas cachés de manera eficiente. Hemos identificado y explorado estos retos desde el punto de vista de las cuatro políticas NUCA: reemplazo, acceso, emplazamiento y migración. En primer lugar nos hemos centrado en la política de reemplazo. La migración de datos permite que los datos que se utilizan más frequentemente se concentren en aquellos bancos que estan más cerca de los cores. Ésto crea grandes diferencias en el uso medio de los bancos en NUCA, siendo los bancos cercanos a los cores los más accedidos, mientras que los bancos lejanos no se acceden tan a menudo. Debido a las diferencias en la frequencia de reemplazos entre bancos, las probabilidades de que el dato expulsado sea reusado en un futuro crecerán o disminuirán dependiendo del banco donde se efectuó el reemplazo. Por otro lado, los trabajos previos en la política de reemplazo no son efectivos en este tipo de cachés ya que los bancos trabajan de manera independiente. Nosotros proponemos tres técnicas de reemplazo para NUCA, siendo The Auction la técnica con mayor beneficio. En cuanto a los retos con la política de acceso, como los datos se pueden mapear en diversos bancos dentro de la caché NUCA, encontrarlos se convierte en una tarea complicada y costosa. Aquí, nosotros proponemos HK-NUCA. Es un algoritmo de acceso que usa el conocimiento integrado en los bancos "home" para reducir de manera eficiente el número medio de accesos necesarios para resolver una petición de memoria. Para analizar la política de emplazamiento, esta tesis muestra la implementación de una caché NUCA híbrida. Nuestra política de emplazamiento permite integrar ambas tecnologías, SRAM y eDRAM, en un único nivel de cache NUCA. Finalmente, en cuanto a la migración en D-NUCA, hemos propuesto The Migration Prefetcher. Es una técnica que permite anticipar migraciones de datos usando el conocimiento adquirido por el historial de accesos. En resumen, esta tesis propone diferentes técnicas para gestionar de manera eficiente las futuras arquitecturas de memoria caché D-NUCA en un entorno CMP. A lo largo de la tesis, demostramos la efectividad de las técnicas propuestas para paliar los efectos inducidos por el hecho de utilizar cachés D-NUCA. Estas técnicas, además de obtener mayor rendimiento que otros mecanismos existentes en la literatura, son en muchos casos más eficientes en términos de energía.

  • Filtering directory lookups in CMPs

     Bosque Arbiol, Ana
    Defense's date: 2011-11-11
    Universidad de Zaragoza
    Theses

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  • Filtering directory lookups in CMPs with write-through caches

     Viñals, Victor; Ibañez, Pablo; Bosque Arbiol, Ana; Llaberia Griño, Jose M.
    International European Conference on Parallel and Distributed Computing
    Presentation's date: 2011-09-02
    Presentation of work at congresses

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  • Filtering directory lookups in CMPs

     Bosque Arbiol, Ana; Viñals Yufera, Victor; IBÁÑEZ MARÍN, PABLO; Llaberia Griño, Jose M.
    Microprocessors and microsystems
    Date of publication: 2011-11
    Journal article

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    Filtering directory lookups in CMPs  Open access

     Bosque, Ana; Viñals Yúfera, Víctor; Ibáñez Marín, Pablo Enrique; Llaberia Griño, Jose M.
    Euromicro Conference on Digital System Design: Architectures, Methods and Tools
    Presentation's date: 2010
    Presentation of work at congresses

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    Coherence protocols consume an important fraction of power to determine which coherence action should take place. In this paper we focus on CMPs with a shared cache and a directory-based coherence protocol implemented as a duplicate of local caches tags. We observe that a big fraction of directory lookups produce a miss since the block looked up is not cached in any local cache. We propose to add a filter before the directory lookup in order to reduce the number of lookups to this structure. The filter identifies whether the current block was last accessed as a data or as an instruction. With this information, looking up the whole directory can be avoided for most accesses. We evaluate the filter in a CMP with 8 in-order processors with 4 threads each and a memory hierarchy with a shared L2 cache.We show that a filter with a size of 3% of the tag array of the shared cache can avoid more than 70% of all comparisons performed by directory lookups with a performance loss of just 0.2% for SPLASH2 and 1.5% for Specweb2005. On average, the number of 15-bit comparisons avoided per cycle is 54 out of 77 for SPLASH2 and 29 out of 41 for Specweb2005. In both cases, the filter requires less than one read of 1 bit per cycle.

  • Non-Speculative Enhancements for the Scheduling Logic

     Gran Tejero, Ruben
    Defense's date: 2010-11-05
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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  • ARQUITECTURA DE COMPUTADORS D'ALTRES PRESTACIONS (CAP)

     Jimenez Castells, Marta; Pericas Gleim, Miquel; Navarro Guerrero, Juan Jose; Llaberia Griño, Jose M.; Llosa Espuny, Jose Francisco; Villavieja Prados, Carlos; Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Ramirez Bellido, Alejandro; Morancho Llena, Enrique; Fernandez Jimenez, Agustin; Pajuelo González, Manuel Alejandro; Olive Duran, Angel; Sanchez Carracedo, Fermin; Moreto Planas, Miquel; Verdu Mula, Javier; Abella Ferrer, Jaume; Valero Cortes, Mateo
    Participation in a competitive project

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    On reducing misspeculations on a pipelined scheduler  Open access

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    IEEE International Parallel and Distributed Processing Symposium
    Presentation's date: 2009-05
    Presentation of work at congresses

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    Pipelining the scheduling logic, which exposes and exploits the instruction level parallelism, degrades processor performance. In a 4-issue processor, our evaluations show that pipelining the scheduling logic over two cycles degrades performance by 10% in SPEC-2000 integer benchmarks. Such a performance degradation is due to sacrificing the ability to execute dependent instructions in consecutive cycles. Speculative selection is a previously proposed technique that boosts the performance of a processor with a pipelined scheduling logic. However, this new speculation source increases the overall number of misspeculated instructions, and this unuseful work wastes energy. In this work we introduce a non-speculative mechanism named Dependence Level Scheduler (DLS)which not only tolerates the scheduling-logic latency but also reduces the number of misspeculated instructions with respect to a scheduler with speculative selection. In DLS, the selection of a group of one-cycle instructions (producer-level) is overlapped with the wake up in advance of its group of dependent instructions. DLS is not speculative because the group of woken in advance instructions will compete for selection only after issuing all producer-level instructions. On average, DLS reduces the number of misspeculated instructions with respect to a speculative scheduler by 17.9%. From the IPC point of view, the speculative scheduler outperforms DLS by 0.3%. Moreover, we propose two non-speculative improvements to DLS.

  • Store Buffer Design for Multibanked Data Caches

     Torres, E; Ibanez, P; Vinals-Yufera, V; Llaberia Griño, Jose M.
    IEEE transactions on computers
    Date of publication: 2009-10
    Journal article

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  • A comparison of two policies for issuing instructions speculatively

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    Journal of systems architecture
    Date of publication: 2007-04
    Journal article

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  • On Reducing Energy-Consumption by Late-Inserting Instructions into the Issue Queue

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    International Symposium on Low Power Electronics and Design
    Presentation's date: 2007-08-29
    Presentation of work at congresses

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  • On Improving a Pipelined Scheduling Logic

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    XVIII Jornadas de Paralelismo. CEDI 2007 II Congreso Español de Informática.
    Presentation of work at congresses

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  • On improving a pipelined scheduling logic

     Ruben, Gran; Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    XVIII Jornadas de Paralelismo. CEDI 2007 II Congreso Español de Informática.
    Presentation of work at congresses

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  • On Tolerating the Scheduling-Loop Latency

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2007-10
    Report

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  • Characterization of Apache web server with Specweb2005

     Bosque, Ana; Ibañez, Pablo; Viñals, Victor; Stenstrom, Per; Llaberia Griño, Jose M.
    MEDEA Workshop MEmory performance: DEaling with Applications, systems and architecture in conjunction with PACT 2007 Conference.
    Presentation of work at congresses

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  • Aceleración del cambio de propietario de un cerrojo en el multiprocesadores DSM

     Rodriguez, Esther; Sahelices, Benjamin; Llanos, Diego R; Ibañez, Pablo; Viñals, Victor; Llaberia Griño, Jose M.
    XVIII Jornadas de Paralelismo. CEDI 2007 II Congreso Español de Informática.
    Presentation of work at congresses

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  • Memory Characterization of Apache using Specweb2005

     Bosque, Ana; Ibañez, Pablo; Viñals, Victor; Stenström, Per; Llaberia Griño, Jose M.
    XVIII Jornadas de Paralelismo. CEDI 2007 II Congreso Español de Informática.
    Presentation of work at congresses

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  • Speeding - Up Synchronizations in DSM Multiprocessors

     Llaberia Griño, Jose M.
    Euro-Par
    Presentation's date: 2006-08-28
    Presentation of work at congresses

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  • Spedding-Up Synchronizations in DSM Multiprocessors

     Dios, A De; Shelices, B; Ibañez, P; Viñals, V; Llaberia Griño, Jose M.
    Euro-Par
    Presentation of work at congresses

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  • Non-Speculative Enhancements for a Pipelined Scheduling Logic

     Llaberia Griño, Jose M.
    Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2006)
    Presentation's date: 2006-07-26
    Presentation of work at congresses

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  • Speeding-Up Synchronizations in DSM Multiprocessors

     Dios, A De; Sahelice, B; Ibañez, P; Viñals, V; Llaberia Griño, Jose M.
    Lecture notes in computer science
    Date of publication: 2006-09
    Journal article

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  • Predicting L2 Misses to Increase Issue-Queue Eficacy

     Llaberia Griño, Jose M.
    4th Workshop on Memory Performance Issues (WMPI-2006) in conjunction with the 12th International Symposium on High-Performance Computer Architecture (HPCA-12)
    Presentation's date: 2006-02-11
    Presentation of work at congresses

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  • An Enhancement for a Sceduling Logic Pipelined over two Cycles

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2006-07
    Report

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  • On Tolerating the Scheduling-Loop Latency Non-Speculatively

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2006-07
    Report

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  • Planificador por Niveles de Dependencia

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2006-10
    Report

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  • La Lógica de Lanzamiento a Ejecución de Instrucciones

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Date: 2006-10
    Report

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  • An Enchancement for a Scheduling Logic Pipelined over two Cycles

     Llaberia Griño, Jose M.
    Jornadas de Paralelismo
    Presentation's date: 2006-09-18
    Presentation of work at congresses

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  • An Enhancement for a Scheduling Logic Pipelined over two Cycles

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    ICCD 2006 XXIV IEEE International Conference on Computer Design
    Presentation of work at congresses

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  • An Enhancement for a Scheduling Logic Pipelined over two Cycles

     Gran Tejero, Ruben; Morancho Llena, Enrique; Olive Duran, Angel; Llaberia Griño, Jose M.
    Jornadas de Paralelismo
    Presentation of work at congresses

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  • Predicting L2 Misses to Increase Issue-Queue Efficacy

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    4th Workshop on Memory Performance Issues (WMPI-2006) in conjunction with the 12th International Symposium on High-Performance Computer Architecture (HPCA-12)
    Presentation of work at congresses

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  • Accurate and complexity-effective coherence predictors

     Bosque, Ana; Viñals, Victor; Llaberia Griño, Jose M.; Stenström, Per
    International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
    Presentation's date: 2005
    Presentation of work at congresses

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  • Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors

     Garzaran, Maria Jesus; Prvulovic, Milos; Llaberia Griño, Jose M.; Viñals, Victor; Rauchweger, Lawrence; Torrellas, Josep
    ACM transactions on architecture and code optimization
    Date of publication: 2005-09
    Journal article

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  • A Mechanism for Verifying Data Speculation

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    Lecture notes in computer science
    Date of publication: 2004-08
    Journal article

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  • Contents Management in First-Level Multibanked Data Caches

     Torres, E F; Ibañez, P; Viñals, V; Llaberia Griño, Jose M.
    Lecture notes in computer science
    Date of publication: 2004-08
    Journal article

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  • El optimizador de bucles del compilador Open64/ORC

     Jimenez Castells, Marta; Fernandez Jimenez, Agustin; Llaberia Griño, Jose M.; Santamaria Barnadas, Eduard
    Date: 2004-12-14
    Report

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  • A Mechanism for Verifying Data Speculation

     Llaberia Griño, Jose M.
    Euro-Par
    Presentation's date: 2004-08-31
    Presentation of work at congresses

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  • Contents Management in First-Level Multibanked Data Caches

     Torres, E F; Ibañez, P; Viñals, V; Llaberia Griño, Jose M.
    Euro-Par
    Presentation of work at congresses

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  • Contents Management in First-Level Multibanked Data Caches

     Llaberia Griño, Jose M.
    Euro-Par
    Presentation's date: 2004-08-31
    Presentation of work at congresses

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  • A Mechanism for Verifying Data Speculation

     Morancho Llena, Enrique; Llaberia Griño, Jose M.; Olive Duran, Angel
    Euro-Par
    Presentation of work at congresses

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  • Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation

     Garzarán, María Jesús; Prvulovic, Milos; Viñals, Victor; Llaberia Griño, Jose M.; Rauchwerger, Lawrence; Torrellas, Josep
    12th International Conference on Parallel Architectures and Compilation Techniques (PACT'03)
    Presentation of work at congresses

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  • Counteractin Bank Misprediction In Sliced First-Level Caches

     Enrique, F Torres; Ibañez, Pablo; Viñals, Victor; Llaberia Griño, Jose M.
    Lecture notes in computer science
    Date of publication: 2003-08
    Journal article

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  • Software Logging under Speculative Parallelization

     Llaberia Griño, Jose M.; Garzazan, Mª Jesus; Prvulovic, Milos; Viñals, Victor; Rauchwerger, Lawrence; Torrellas, Josep
    Date of publication: 2003-12-31
    Book chapter

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  • Counteracting Bank Misprediction in Sliced First-Level Caches

     Llaberia Griño, Jose M.
    Euro-Par
    Presentation's date: 2003-08-26
    Presentation of work at congresses

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