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1 to 50 of 1116 results
 
  • Extending the Applicability of Deterministic Multithreading

     Nowack, V.
    Universitat Politècnica de Catalunya
    Theses
  • Hardware Thread Scheduling Algorithms for Single-ISA Asymmetric CMPs  Open access

     Markovic, N.
    Universitat Politècnica de Catalunya
    Theses
  • Seymour Cray

     Valero, M.
    Award or recognition
  • Euro-Par

     Valero, M.
    Award or recognition
  • AXIOM

     Valero, M.; Navarro, Nacho; Martorell, X.; Jimenez, D.; Alvarez, C.
    Competitive project
  • VSR sort: a novel vectorised sorting algorithm and architecture extensions for future microprocessors

     Hayes, T.; Palomar, O.; Unsal, O.; Cristal, A.; Valero, M.
    International Symposium on High-Performance Computer Architecture
    p. 26-38
    DOI: 10.1109/HPCA.2015.7056019
    Presentation's date: 2015-02
    Presentation of work at congresses
  • Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM Power7  Open access

     Prat, D.; Ortega, C.; Casas, M.; Moreto, M.; Valero, M.
    International Workshop on Adaptive Self-tuning Computing Systems
    p. 1-6
    Presentation's date: 2015-01-21
    Presentation of work at congresses
    Access to the full text
  • PAMS: pattern aware memory system for embedded systems

     Hussain, T.; Sonmez, N.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M.; Gursal, S.
    International Conference on ReConFigurable Computing and FPGAs
    p. 1-7
    DOI: 10.1109/ReConFig.2014.7032544
    Presentation's date: 2014-12-09
    Presentation of work at congresses
  • Consolider-ingenio 2014 Supercomputación y e-Ciencia

     Valero, M.; Monreal, T.
    Competitive project
  • AMMC: advance multi-core memory controller  Open access

     Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M.
    International Conference on Field-Programmable Technology
    p. 292-295
    DOI: 10.1109/FPT.2014.7082802
    Presentation's date: 2014-12
    Presentation of work at congresses
    Access to the full text
  • Hybrid cache designs for reliable hybrid high and ultra-low voltage operation

     Maric, B.; Abella, J.; Cazorla, F.J.; Valero, M.
    ACM transactions on design automation of electronic systems
    Vol. 20, num. 1, p. Article No. 10-
    DOI: 10.1145/2658988
    Date of publication: 2014-11-01
    Journal article
  • Analyzing the efficiency of L1 caches for reliable hybrid-voltage operation using EDC codes

     Maric, B.; Abella, J.; Valero, M.
    IEEE transactions on very large scale integration (VLSI) systems
    Vol. 22, num. 10, p. 2211-2215
    DOI: 10.1109/TVLSI.2013.2282498
    Date of publication: 2014-10-01
    Journal article
  • DeTrans: Deterministic and parallel execution of transactions

     Smiljkovic, V.; Stipic, S.; Fetzer, C.; Unsal, O.; Cristal, A.; Valero, M.
    International Symposium on Computer Architecture and High Performance Computing
    p. 152-159
    DOI: 10.1109/SBAC-PAD.2014.20
    Presentation's date: 2014-10
    Presentation of work at congresses
  • Characterizing the communications demands of the Graph500 benchmark on a commodity cluster

     Fuentes, P.; Bosque, J.; Beivide, R.; Valero, M.; Minkenberg, C.
    International Symposium on Big Data Computing
    Presentation's date: 2014-09-12
    Presentation of work at congresses
  • MAPC: memory access pattern based controller

     Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M.
    International Conference on Field Programmable Logic and Applications
    p. 1-4
    DOI: 10.1109/FPL.2014.6927397
    Presentation's date: 2014-09
    Presentation of work at congresses
  • DReAM: Per-task DRAM energy metering in multicore systems

     Liu, Q.; Moreto, M.; Abella, J.; Cazorla, F.; Valero, M.
    International Conference on Parallel and Distributed Computing
    p. 111-123
    DOI: 10.1007/978-3-319-09873-9-10
    Presentation's date: 2014-08
    Presentation of work at congresses
  • Techniques for Improving the Performance of Software Transactional Memory  Open access

    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Per-task Energy Accounting in Computing Systems

     Liu, Q.; Jiménez, V.; Moreto, M.; Abella, J.; Cazorla, F.; Valero, M.
    IEEE computer architecture letters
    Vol. 13, num. 2, p. 85-88
    DOI: 10.1109/L-CA.2013.24
    Date of publication: 2014-07-01
    Journal article
  • Advanced pattern based memory controller for FPGA based HPC applications

     Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M.
    International Conference on High Performance Computing & Simulation
    p. 287-294
    DOI: 10.1109/HPCSim.2014.6903697
    Presentation's date: 2014-07
    Presentation of work at congresses
  • Dynamic-vector execution on a general purpose EDGE chip multiprocessor

     Duric, M.; Palomar, O.; Smith, A.; Stanic, M.; Unsal, O.; Cristal, A.; Valero, M.; Burger, D.; Veidenbaum, A.V.
    International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
    p. 18-25
    DOI: 10.1109/SAMOS.2014.6893190
    Presentation's date: 2014-07
    Presentation of work at congresses
  • Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi

     Stanic, M.; Palomar, O.; Ratkovic, I.; Duric, M.; Unsal, O.; Cristal, A.; Valero, M.
    International Conference on High Performance Computing & Simulation
    p. 47-54
    DOI: 10.1109/HPCSim.2014.6903668
    Presentation's date: 2014-07
    Presentation of work at congresses
  • Physical vs. physically-aware estimation flow: case study of design space exploration of adders

     Ratkovic, I.; Palomar, O.; Stanic, M.; Unsal, O.; Cristal, A.; Valero, M.
    IEEE Computer Society Annual Symposium on VLSI
    p. 118-123
    DOI: 10.1109/ISVLSI.2014.14
    Presentation's date: 2014-07
    Presentation of work at congresses
  • PVMC: programmable vector memory controller

     Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M.
    International Conference on Application-Specific Systems, Architectures and Processors
    p. 240-247
    DOI: 10.1109/ASAP.2014.6868668
    Presentation's date: 2014-06-18
    Presentation of work at congresses
  • Enabling preemptive multiprogramming on GPUs  Open access

     Tanasic, I.; Gelado, I.; Cabezas, J.; Alex Ramirez; Navarro, Nacho; Valero, M.
    International Symposium on Computer Architecture
    p. 193-204
    DOI: 10.1109/ISCA.2014.6853208
    Presentation's date: 2014-06-14
    Presentation of work at congresses
    Access to the full text
  • Author retrospective for "Software trace cache"  Open access

     Alex Ramirez; Falcon, A.; Santana, O.; Valero, M.
    International Conference on Supercomputing
    p. 45-47
    DOI: 10.1145/2591635.2594508
    Presentation's date: 2014-06-10
    Presentation of work at congresses
    Access to the full text
  • Automatic exploration of potential parallelism in sequential applications

     Subotic, V.; Ayguade, E.; Labarta, J.; Valero, M.
    International Conference on Supercomputing
    p. 156-171
    DOI: 10.1007/978-3-319-07518-1-10
    Presentation's date: 2014-06
    Presentation of work at congresses
  • CPU Accounting in Multi-Threaded Processors  Open access

     Ruiz, J.
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Scalable System Software for High Performance Large-scale Applications  Open access

    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Colegiado honor del COEINF

     Valero, M.
    Award or recognition
  • Scaling irregular applications through data aggregation and software multithreading

     Morari, A.; Tumeo, A.; Chavarria, D.; Villa, O.; Valero, M.
    IEEE International Parallel and Distributed Processing Symposium
    p. 1126-1135
    DOI: 10.1109/IPDPS.2014.117
    Presentation's date: 2014-05
    Presentation of work at congresses
  • Dynamic transaction coalescing

     Stipic, S.; Karakostas, V.; Smiljkovic, V.; Gajinov, V.; Unsal, O.; Cristal, A.; Valero, M.
    ACM International Conference on Computing Frontiers
    p. Article No. 18-
    DOI: 10.1145/2597917.2597930
    Presentation's date: 2014-05
    Presentation of work at congresses
  • Stand-alone memory controller for graphics system

     Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M.; Haider, A.
    International Symposium on Applied Reconfigurable Computing
    p. 108-120
    DOI: 10.1007/978-3-319-05960-0_10
    Presentation's date: 2014-04
    Presentation of work at congresses
  • EVX: vector execution on low power EDGE cores

     Duric, M.; Palomar, O.; Smith, A.; Unsal, O.; Cristal, A.; Valero, M.; Burger, D.
    Design, Automation and Test in Europe
    p. 1-4
    DOI: 10.7873/DATE.2014.035
    Presentation's date: 2014-03-24
    Presentation of work at congresses
  • Premio de Honor de la ACET

     Valero, M.
    Award or recognition
  • Using dynamic runtime testing for rapid development of architectural simulators

     Tomic, S.; Cristal, A.; Unsal, O.; Valero, M.
    International journal of parallel programming
    Vol. 42, num. 1, p. 119-139
    DOI: 10.1007/s10766-012-0208-7
    Date of publication: 2014-02-01
    Journal article
  • APMC: advanced pattern based memory controller

     Hussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M.; Rethinagiri, S.
    ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
    p. 252
    DOI: 10.1145/2554688.2554732
    Presentation's date: 2014-02
    Presentation of work at congresses
  • Arquitectura de Computadors d'Altes Prestacions (ACAP)

     Olive, A.; Alex Ramirez; Llosa, J.; Sanchez, F.; Jimenez, M.; Fernandez, A.; Jimenez, D.; Alvarez, C.; Morancho, E.; Moreto, M.; Palomar, O.; Carpenter, P.; Monreal, T.; Valero, M.
    Competitive project
  • Runtime-aware architectures: a first approach

     Valero, M.; Moreto, M.; Casas, M.; Ayguade, E.; Labarta, J.
    Supercomputing frontiers and innovations
    Vol. 1, num. 1, p. 29-44
    DOI: 10.14529/jsfi140102
    Date of publication: 2014
    Journal article
  • CODOMs: Protecting software with code-centric memory domains

     Vilanova, L.; Ben-Yehuda, M.; Navarro, N.; Etsion, Y.; Valero, M.
    International Symposium on Computer Architecture
    p. 469-480
    DOI: 10.1109/ISCA.2014.6853202
    Presentation's date: 2014
    Presentation of work at congresses
  • VALib and SimpleVector: Tools for rapid initial research on vector architectures

     Stanic, M.; Palomar, O.; Ratkovic, I.; Duric, M.; Unsal, O.; Cristal, A.; Valero, M.
    ACM International Conference on Computing Frontiers
    DOI: 10.1145/2597917.2597919
    Presentation's date: 2014
    Presentation of work at congresses
  • Profile-guided transaction coalescing—lowering transactional overheads by merging transactions

     Stipic, S.; Smiljkovic, V.; Unsal, O.; Cristal, A.; Valero, M.
    ACM transactions on architecture and code optimization
    Vol. 10, num. 4, p. Article No. 50-
    DOI: 10.1145/2541228.2555306
    Date of publication: 2013-12
    Journal article
  • Thread assignment of multithreaded network applications in multicore/multithreaded processors

     Radojkovic, P.; Cakarevic, V.; Verdu, J.; Pajuelo, M.A.; Cazorla, F.; Nemirovsky, M.; Valero, M.
    IEEE transactions on parallel and distributed systems
    Vol. 24, num. 12, p. 2513-2525
    DOI: 10.1109/TPDS.2012.311
    Date of publication: 2013-12
    Journal article
  • Hardware support for accurate per-task energy metering in multicore systems

     Liu, Q.; Moreto, M.; Jiménez, V.; Abella, J.; Cazorla, F.; Valero, M.
    ACM transactions on architecture and code optimization
    Vol. 10, num. 4, p. 34:1-34:27
    DOI: 10.1145/2555289.2555291
    Date of publication: 2013-12
    Journal article
  • Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?

     Rajovic, N.; Carpenter, P.; Gelado, I.; Puzovic, N.; Alex Ramirez; Valero, M.
    International Conference for High Performance Computing, Networking, Storage and Analysis
    p. Article No. 40-
    DOI: 10.1145/2503210.2503281
    Presentation's date: 2013-12
    Presentation of work at congresses
  • Programmability and portability for exascale: top down programming methodology and tools with StarSs

     Subotic, V.; Brinkmann, S.; Marjanovic, V.; Badia, R.M.; Gracia, J.; Niethammer, C.; Ayguade, E.; Labarta, J.; Valero, M.
    Journal of computational science
    Vol. 4, num. 6, p. 450-456
    DOI: 10.1016/j.jocs.2013.01.008
    Date of publication: 2013-11
    Journal article
  • The TERAFLUX Project: Exploiting the dataflow paradigm in next generation teradevices

     Solinas, M.; Badia, R.M.; Bodin, F.; Cohen, A.; Evripidou, P.; Faraboschi, P.; Fechner, B.; Gao, G.; Garbade, A.; Girbal, S.; Goodman, D.; Khan, B.; Koliai, S.; Li, F.; Lujan, M.; Morin, L.; Mendelson, A.; Navarro, Nacho; Pop, A.; Trancoso, P.; Ungerer, T.; Valero, M.; Weis, S.; Watson, I.; Zuckermann, S.; Giorgi, R.
    Euromicro Symposium on Digital Systems Design
    p. 272-279
    DOI: 10.1109/DSD.2013.39
    Presentation's date: 2013-09
    Presentation of work at congresses