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  • Using dynamic runtime testing for rapid development of architectural simulators

     Tomic, Sa¿a; Cristal Kestelman, Adrian; Unsal, Osman Sabri; Valero Cortes, Mateo
    International journal of parallel programming
    Date of publication: 2014-02-01
    Journal article

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    Architectural simulator platforms are particularly complex and error-prone programs that aim to simulate all hardware details of a given target architecture. Development of a stable cycle-accurate architectural simulator can easily take several man-years. Discovering and fixing all visible errors in a simulator often requires significant effort, much higher than for writing the simulator code in the first place. In addition, there are no guarantees that all programming errors will be eliminated, no matter how much effort is put into testing and debugging. This paper presents dynamic runtime testing, a methodology for rapid development and accurate detection of functional bugs in architectural cycle-accurate simulators. Dynamic runtime testing consists of comparing an execution of a cycle-accurate simulator with an execution of a simple and functionally equivalent emulator. Dynamic runtime testing detects a possible functional error if there is a mismatch between the execution in the simulator and the emulator. Dynamic runtime testing provides a reliable and accurate verification of a simulator, during its entire development cycle, with very acceptable performance impact, and without requiring complex setup for the simulator execution. Based on our experience, dynamic testing reduced the simulator modification time from 12-18 person-months to only 3-4 person-months, while it only modestly reduced the simulator performance (in our case under 20 %). © 2012 Springer Science+Business Media, LLC.

  • Scalable System Software for High Performance Large-scale Applications  Open access

     Morari, Alessandro
    Defense's date: 2014-05-27
    Universitat Politècnica de Catalunya
    Theses

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    En las últimas décadas, los sistemas a gran escala de alto rendimiento han sido una herramienta fundamental para el descubrimiento científico y la ingeniería. El crecimiento de las peformance los supercomputadores y la consiguiente reducción de los costes han hecho que esta tecnología sea disponible para un gran número de científicos e ingenieros que trabajan en muchos problemas diferentes . El diseño de la próxima generación de supercomputadoras incluirán requisitos de High Perfomance Computing (HPC) tradicionales, así como los nuevos requisitos para manejar gran volumen de datos. Las aplicaciones de datos intensivos juegan un papel importante en una variedad de campos, y son el foco actual de varias líneas de investigación en HPC.Debido a los retos de escalabilidad y eficiencia, la próxima generación de superordenadores necesita un rediseño de todo lo stack del software. Se espera que el software del sistema va a cambiar drásticamente para adaptarse al próximo hardware y para satisfacer las nuevas necesidades de las aplicaciónes.Esta tesis doctoral estudia la escalabilidad del software del sistema. La tesis se inicia en el nivel de sistema operativo: primero estudia un OS general-purpose (Linux) y luego estudia light-weight kernels ( CNK ). A continuación, la tesi estudia el runtime system: implementamos un runtime system para sistemas de memoria distribuida que incluye muchos de los servicios de sistema requeridos por aplicaciones de próxima generación. Por fin, estudiamo las características hardware que pueden ser explotadas a nivel de usuario para mejorar las applicaciones, y potencialmente incluir estas en nuestro runtime system.Las contribuciones de esta tesis son las siguientes :Escalabilidad del sistema operativo: Proporcionamos un estudio preciso de los problemas de escalabilidad de los sistemas operativos modernos para HPC. Diseñamos y implementamos una metodología donde la información cuantitativa detallada puede ser obtenida para cada evento de OS noise. Validamos nuestro enfoque comparándolo con otras técnicas convencionales bien conocidas para analizar el ruido del sistema operativo, tales FTQ ( Fixed Time Quantum ) . Evaluación de la gestión de la TLB para un lightweight kernel: proporcionamos una evaluación del TLB handling - asignación de memoria dinámica, la asignación de memoria estática con las entradas de la TLB reemplazables , y asignación de memoria estática con las entradas de la TLB fijas (no TLB misses ) en un sistema IBM Blue Gene / P.Escalabilidad del runtime system : Diseñamos e implementamos un runtime system con todas las funciones y el modelo de programación para ejecutar aplicaciones irregulares en un clúster. El runtime system es una libreria llamad Global Memory and Threading ( GMT) y integra un modelo de comunicación PGAS y una estructura de programa fork/join. El runtime system usa aggregacion par cubrir la larencia de red. Comparamos GMT con otros modelos PGAS , con codigo MPI optimizado a mano y arquitecturas personalizadas ( Cray XMT) sobreun conjunto de aplicaciones irregulares a gran escala: breadth first search , random walk y concurrent hashamp. Nuestro runtime es órdenes de magnitud superior a otras soluciones para cluster systems con arquiectura similare.Escalabilidad de nivel de usuario explotando características del hardware : Mostramos la alta complejidad de las optimizaciones de hardware de bajo nivel como una motivación para incorporar esta lógica en un runtime system. Evaluamos los efectos de mecanismo de hardware-thread priority que controla la velocidad a la que cada hilo de clock decodifica la instrucciónes sobre IBM POWER5 y POWER6 . Finalmente, mostramos cómo se puede explotar eficazmente la localidad de caché y de network-on-chip en una arquitectura Tilera many-core para mejorar la escalabilidad intra-core.

    In the last decades, high-performance large-scale systems have been a fundamental tool for scientific discovery and engineering advances. The sustained growth of supercomputing performance and the concurrent reduction in cost have made this technology available for a large number of scientists and engineers working on many different problems. The design of next-generation supercomputers will include traditional HPC requirements as well as the new requirements to handle data-intensive computations. Data intensive applications will hence play an important role in a variety of fields, and are the current focus of several research trends in HPC. Due to the challenges of scalability and power efficiency, next-generation of supercomputers needs a redesign of the whole software stack. Being at the bottom of the software stack, system software is expected to change drastically to support the upcoming hardware and to meet new application requirements. This PhD thesis addresses the scalability of system software. The thesis start at the Operating System level: first studying general-purpose OS (ex. Linux) and then studying lightweight kernels (ex. CNK). Then, we focus on the runtime system: we implement a runtime system for distributed memory systems that includes many of the system services required by next-generation applications. Finally we focus on hardware features that can be exploited at user-level to improve applications performance, and potentially included into our advanced runtime system. The thesis contributions are the following: Operating System Scalability: We provide an accurate study of the scalability problems of modern Operating Systems for HPC. We design and implement a methodology whereby detailed quantitative information may be obtained for each OS noise event. We validate our approach by comparing it to other well-known standard techniques to analyze OS noise, such FTQ (Fixed Time Quantum). Evaluation of the address translation management for a lightweight kernel: we provide a performance evaluation of different TLB management approaches ¿ dynamic memory mapping, static memory mapping with replaceable TLB entries, and static memory mapping with fixed TLB entries (no TLB misses) on a IBM BlueGene/P system. Runtime System Scalability: We show that a runtime system can efficiently incorporate system services and improve scalability for a specific class of applications. We design and implement a full-featured runtime system and programming model to execute irregular appli- cations on a commodity cluster. The runtime library is called Global Memory and Threading library (GMT) and integrates a locality-aware Partitioned Global Address Space communication model with a fork/join program structure. It supports massive lightweight multi-threading, overlapping of communication and computation and small messages aggregation to tolerate network latencies. We compare GMT to other PGAS models, hand-optimized MPI code and custom architectures (Cray XMT) on a set of large scale irregular applications: breadth first search, random walk and concurrent hash map access. Our runtime system shows performance orders of magnitude higher than other solutions on commodity clusters and competitive with custom architectures. User-level Scalability Exploiting Hardware Features: We show the high complexity of low-level hardware optimizations for single applications, as a motivation to incorporate this logic into an adaptive runtime system. We evaluate the effects of controllable hardware-thread priority mechanism that controls the rate at which each hardware-thread decodes instruction on IBM POWER5 and POWER6 processors. Finally, we show how to effectively exploits cache locality and network-on-chip on the Tilera many-core architecture to improve intra-core scalability.

  • Techniques for Improving the Performance of Software Transactional Memory  Open access

     Stipic, Srdan
    Defense's date: 2014-07-21
    Universitat Politècnica de Catalunya
    Theses

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    Transactional Memory (TM) da al desallorador de software la oportunidad de escribir programas concurenter mas facil comparado con todos los paradigmas de programacion previas y da la rendimiento comarable a lock-based sincronisaciones.Actuales Software TM (STM) implementaciones tienen gastos generales de rendimiento que se pueden reducir con la intoduccion de nuevas abstracciones enTransactional Memory modelo de programacion.En la tesis, presentamos cuatro nuevas tecnicas para mejorar el rendimiento de Software TM: (i) Abstract Nested Transactions (ANT), (ii) TagTM, (iii) profile-guided transaction coalescing, and (iv) dynamic transaction coalescing.ANT mejora el rendimiento de aplicaciones transaccionales si romper la semantica de paradigma transaccional, TagTM accelera los accesos a meta-data transaccional,profile-guided transaction coalescing baja gastos generales transaccionales en tiempo de compilacion, y dynamic transaction coalescing baja gastos generales transaccionales en tiempo de ejecucion.Nuestra analisis muestra que Abstract Nested Transactions, TagTM, profile-guided transaction coalescing, y dynamic transaction coalescing mejoran el rendimiento de los programas originales que utilisan Software Transactional Memory.

    Transactional Memory (TM) gives software developers the opportunity to write concurrent programs more easily compared to any previous programming paradigms and gives a performance comparable to lock-based synchronizations. Current Software TM (STM) implementations have performance overheads that can be reduced by introducing new abstractions in Transactional Memory programming model. In this thesis we present four new techniques for improving the performance of Software TM: (i) Abstract Nested Transactions (ANT), (ii) TagTM, (iii) profile-guided transaction coalescing, and (iv) dynamic transaction coalescing. ANT improves performance of transactional applications without breaking the semantics of the transactional paradigm, TagTM speeds up accesses to transactional meta-data, profile-guided transaction coalescing lowers transactional overheads at compile time, and dynamic transaction coalescing lowers transactional overheads at runtime. Our analysis shows that Abstract Nested Transactions, TagTM, profile-guided transaction coalescing, and dynamic transaction coalescing improve the performance of the original programs that use Software Transactional Memory.

  • CPU Accounting in Multi-Threaded Processors  Open access

     Ruiz Luque, Jose Carlos
    Defense's date: 2014-05-29
    Universitat Politècnica de Catalunya
    Theses

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    En los últimos años, los procesadores multihilo se han convertido más y más populares en la industria con el fin de aumentar el rendimiento del sistema y de cada aplicación, superando las limitaciones impuestas por el limitado paralelismo a nivel de instrucciones y por las restricciones de potencia y térmica. Los procesadores multihilo son ampliamente utilizados en servidores, ordenadores de sobremesa, ordenadores portátiles y dispositivos móviles.Sin embargo, los procesadores multihilo introducen complejidades en la medición de la capacidad del procesador, ya que la capacidad del procesador medida a una aplicación no sólo depende del tiempo que la aplicación está ejecutándose en un procesador, pero también de la cantidad de los recursos hardware que recibe durante ese intervalo. Y dado que en un procesador multihilo, los recursos hardware son compartidos dinámicamente entre las aplicaciones, la capacidad del procesador medida a una aplicación depende de las aplicaciones que se ejecutan concurrentemente en el procesador. Esto es un inconveniente debido a que la medición de la capacidad del procesador de la misma aplicación con el mismo conjunto de datos de entrada puede ser medida significativamente diferente dependiendo de la carga de trabajo en el que se ejecuta. El uso de sistemas con mecanismos precisos de medida de la capacidad del procesador es necesario para mejor el uso justo del sistema entre las aplicaciones en el sistema. Además, permite a los usuarios ser cargado justamente en centro de datos compartidos, facilitando la consolidación de servidores en sistemas futuros.Esta tesis analiza los conceptos de capacidad del procesador y medida de la capacidad del procesador para procesadores multihilo. En este estudio, nosotros mostramos que los mecanismos actuales de medida de la capacidad del procesador no son tan precisos que deberían ser en procesadores multihilo. Por esta razón, nosotros presentamos dos novedosos mecanismos hardware de medida de la capacidad del procesador que mejora la precisión en la medición de la capacidad de procesador en procesadores multihilo con un bajo coste hardware. Nosotros nos centramos en diferentes tipos de arquitectura de procesadores multihilo tales como procesadores multinúcleo y procesadores multinúcleo que cada núcleo soporta multihilo. Finalmente, nosotros analizamos el impacto de los recursos hardware compartidos en los procesadores multihilo en el planificador del procesador en el sistema operativo y proponemos varios modelos de planificador que mejora el conocimiento de los recursos hardware compartidos.

    In recent years, multi-threaded processors have become more and more popular in industry in order to increase the system aggregated performance and per-application performance, overcoming the limitations imposed by the limited instruction-level parallelism, and by power and thermal constraints. Multi-threaded processors are widely used in servers, desktop computers, lap-tops, and mobile devices. However, multi-threaded processors introduce complexities when accounting CPU (computation) capacity (CPU accounting), since the CPU capacity accounted to an application not only depends upon the time that the application is scheduled onto a CPU, but also on the amount of hardware resources it receives during that period. And given that in a multi-threaded processor hardware resources are dynamically shared between applications, the CPU capacity accounted to an application in a multi-threaded processor depends upon the workload in which it executes. This is inconvenient because the CPU accounting of the same application with the same input data set may be accounted significantly different depending upon the workload in which it executes. Deploying systems with accurate CPU accounting mechanisms is necessary to increase fairness among running applications. Moreover, it will allow users to be fairly charged on a shared data center, facilitating server consolidation in future systems. This Thesis analyses the concepts of CPU capacity and CPU accounting for multi-threaded processors. In this study, we demonstrate that current CPU accounting mechanisms are not as accurate as they should be in multi-threaded processors. For this reason, we present two novel CPU accounting mechanisms that improve the accuracy in measuring the CPU capacity for multi-threaded processors with low hardware overhead. We focus our attention on several current multi-threaded processors, including chip multiprocessors and simultaneous multithreading processors. Finally, we analyse the impact of shared resources in multi-threaded processors in operating system CPU scheduler and we propose several schedulers that improve the knowledge of shared hardware resources at the software level.

  • Hardware support for accurate per-task energy metering in multicore systems

     Liu, Qixiao; Moreto Planas, Miquel; Jiménez, Víctor; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortes, Mateo
    ACM transactions on architecture and code optimization
    Date of publication: 2013-12
    Journal article

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    Accurately determining the energy consumed by each task in a system will become of prominent importance in future multicore-based systems because it offers several benefits, including (i) better application energy/performance optimizations, (ii) improved energy-aware task scheduling, and (iii) energy-aware billing in data centers. Unfortunately, existing methods for energy metering in multicores fail to provide accurate energy estimates for each task when several tasks run simultaneously. This article makes a case for accurate Per-Task Energy Metering (PTEM) based on tracking the resource utilization and occupancy of each task. Different hardware implementationswith different trade-offs between energy prediction accuracy and hardware-implementation complexity are proposed. Our evaluation shows that the energy consumed in a multicore by each task can be accurately measured. For a 32-core, 2-way, simultaneous multithreaded core setup, PTEM reduces the average accuracy error from more than 12% when our hardware support is not used to less than 4% when it is used. The maximum observed error for any task in the workload we used reduces from 58% down to 9% when our hardware support is used.

  • SMT malleability in IBM POWER5 and POWER6 processors

     Morari, A.; Boneti, Carlos; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Cher, Chen-Yong; Buyuktosunoglu, Alper; Bose, Prosenjit; Valero Cortes, Mateo
    IEEE transactions on computers
    Date of publication: 2013-04
    Journal article

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    While several hardware mechanisms have been proposed to control the interaction between hardware threads in an SMT processor, few have addressed the issue of software-controllable SMT performance. The IBM POWER5 and POWER6 are the first high-performance processors implementing a software-controllable hardware-thread prioritization mechanism that controls the rate at which each hardware-thread decodes instructions. This paper shows the potential of this basic mechanism to improve several target metrics for various applications on POWER5 and POWER6 processors. Our results show that although the software interface is exactly the same, the software-controlled priority mechanism has a different effect on POWER5 and POWER6. For instance, hardware threads in POWER6 are less sensitive to priorities than in POWER5 due to the in order design. We study the SMT thread malleability to enable user-level optimizations that leverage software-controlled thread priorities...

  • Thread assignment of multithreaded network applications in multicore/multithreaded processors

     Radojkovic, Petar; Cakarevic, Vladimir; Verdu Mula, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortes, Mateo
    IEEE transactions on parallel and distributed systems
    Date of publication: 2013-12
    Journal article

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    The introduction of multithreaded processors comprised of a large number of cores with many shared resources makes thread scheduling, and in particular optimal assignment of running threads to processor hardware contexts to become one of the most promising ways to improve the system performance. However, finding optimal thread assignments for workloads running in state-of-the-art multicore/multithreaded processors is an NP-complete problem. In this paper, we propose BlackBox scheduler, a systematic method for thread assignment of multithreaded network applications running on multicore/multithreaded processors. The method requires minimum information about the target processor architecture and no data about the hardware requirements of the applications under study. The proposed method is evaluated with an industrial case study for a set of multithreaded network applications running on the UltraSPARC T2 processor. In most of the experiments, the proposed thread assignment method detected the best actual thread assignment in the evaluation sample. The method improved the system performance from 5 to 48 percent with respect to load balancing algorithms used in state-of-the-art OSs, and up to 60 percent with respect to a naive thread assignment.

  • Fair CPU time accounting in CMP+SMT processors

     Luque, Carlos; Moreto Planas, Miquel; Cazorla, Francisco J.; Valero Cortes, Mateo
    ACM transactions on architecture and code optimization
    Date of publication: 2013-01
    Journal article

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  • Moving from petaflops to petadata

     Flynn, Michael J.; Mencer, Oskar; Milutinovic, Veljko; Rakocevic, Goran; Stenstrom, Per; Trobec, Roman; Valero Cortes, Mateo
    Communications of the ACM
    Date of publication: 2013-05
    Journal article

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    The race to build ever-faster supercomputers is on, with more contenders than ever before. However, the current goals set for this race may not lead to the fastest computation for particular applications.

  • Programmability and portability for exascale: top down programming methodology and tools with StarSs

     Subotic, Vladimir; Brinkmann, Steffen; Marjanovic, Vladimir; Badia Sala, Rosa Maria; Gracia, Jose; Niethammer, Chirstoph; Ayguade Parra, Eduard; Labarta Mancho, Jesus Jose; Valero Cortes, Mateo
    Journal of computational science
    Date of publication: 2013-11
    Journal article

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    StarSs is a task-based programming model that allows to parallelize sequential applications by means of annotating the code with compiler directives. The model further supports transparent execution of designated tasks on heterogeneous platforms, including clusters of GPUs. This paper focuses on the methodology and tools that complements the programming model forming a consistent development environment with the objective of simplifying the live of application developers. The programming environment includes the tools TAREADOR and TEMANEJO, which have been designed specifically for StarSs. TAREADOR, a Valgrind-based tool, allows a top-down development approach by assisting the programmer in identifying tasks and their data-dependencies across all concurrency levels of an application. TEMANEJO is a graphical debugger supporting the programmer by visualizing the task dependency tree on one hand, but also allowing to manipulate task scheduling or dependencies. These tools are complemented with a set of performance analysis tools (Scalasca, Cube and Paraver) that enable to fine tune StarSs application.

  • ACM Awards

     Valero Cortes, Mateo
    Award or recognition

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  • Computación de Altas Prestaciones VI

     Valero Cortes, Mateo
    Participation in a competitive project

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  • Raising the Level of Abstraction: Simulation of Large Chip Multiprocessors Running Multithreaded Applications  Open access

     Rico Carro, Alejandro
    Defense's date: 2013-10-29
    Universitat Politècnica de Catalunya
    Theses

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    El nombre de transistors en els circuits integrats continua doblant-se cada dos anys. Aquest nombre creixent de transistors s'utilitza per integrar més nuclis de processament en el mateix chip. No obstant això, degut a la densitat de potència i la disminució de guanys per l'explotació de paral·lelisme a nivell d'instrucció, el rendiment d'un sol fil en un nucli no es dobla cada dos anys, sinó cada tres anys i mig.La investigació en arquitectura de computadors està principalment basada en simulació. En els simuladors d'arquitectura de computadors, la complexitat de la màquina simulada incrementa amb el nombre de transistors disponibles. Quant més transistors, més nuclis, i més complexe és el model. No obstant això, el rendiment dels simuladors d'arquitectura de computadors depèn del rendiment d'un sol fil a la màquina que executa el simulador i, com hem dit abans, aquest no es dobla cada dos anys, sinó cada tres anys i mig. Aquesta diferència creixent entre la complexitat de la màquina simulada i la velocitat de simulació és el que anomenem la bretxa de la velocitat de simulació.Degut a la bretxa de la velocitat de simulació, els simuladors d'arquitectura de computadors són cada cop més lents. La simulació d'una aplicació de referència pot trigar setmanes o inclús mesos. Els investigadors són conscients d'aquest problema i han estat proposant tècniques per reduir el temps de simulació. Aquestes tècniques inclouen l'ús de conjunt d'entrades d'aplicació reduïts, simulació mostrejada i paral·lelització.Un altra tècnica per reduir el temps de simulació és elevar el nivell d'abstracció del model simulat. En aquesta tesi advoquem per aquesta estratègia. Primer, decidim utilitzar simulació basada en traces perquè no necessita proporcionar simulació funcional i, per tant, permet elevar el nivell d'abstracció més enllà de la representació a nivell d'instrucció.No obstant això, la simulació basada en traces té algunes limitacions. La més important d'aquestes és que no pot reproduir el comportament dinàmic de les aplicacions multifil. En aquesta tesi, proposem una metodologia de simulació que utilitza simulació basada en traces conjuntament amb un sistema en temps d'execució que permet una simulació correcta d'aplicacions multifil al reproduir el comportament depenent del rendiment en temps d'execució.Amb aquesta metodologia, avaluem l'ús de múltiples nivells d'abstracció per reduir el temps de simulació, des d'un mode de simulació a nivell d'aplicació fins a un mode detallat a nivell d'instrucció. Fem una avaluació exhaustiva de l'impacte en la precisió i velocitat de simulació d'aquests nivells d'abstracció i també mostrem la seva aplicabilitat i utilitat depenent de les avaluacions que es volen portar a terme. També comparem aquest nivell d'abstracció amb els emprats en els simuladors d'arquitectura de computadors més populars. A més, validem el nivell d'abstracció més alt contra la màquina real.Un dels nivells d'abstracció interessants per la simulació d'arquitectures multi-nucli és el mode de memòria. Aquest mode és capaç de modelar el rendiment d'un nucli superescalar fora d'ordre utilitzant traces d'accessos a memòria. A aquest nivell d'abstracció, treballs previs han utilitzat traces filtrades que no inclouen encerts en la memòria cau de primer nivell, i permeten simular només els accessos al segon nivell per simulacions d'un sol fil. No obstant això, simular aplicacions multifil utilitzant traces filtrades igual que en treballs previs comporta algunes imprecisions. Nosaltres proposem una tècnica per reduir aquestes imprecisions i avaluem el guany en velocitat, la seva aplicabilitat i utilitat per simulacions a nivell de memòria.En conjunt, aquesta tesi contribueix al coneixement amb tècniques per la simulació de chips multiprocessador amb centenars de nuclis utilitzant traces, alhora que estableix i avalua els compromisos d'utilitzar diversos nivells d'abstracció en termes de precisió i velocitat de simulació.

    The number of transistors on an integrated circuit keeps doubling every two years. This increasing number of transistors is used to integrate more processing cores on the same chip. However, due to power density and ILP diminishing returns, the single-thread performance of such processing cores does not double every two years, but doubles every three years and a half. Computer architecture research is mainly driven by simulation. In computer architecture simulators, the complexity of the simulated machine increases with the number of available transistors. The more transistors, the more cores, the more complex is the model. However, the performance of computer architecture simulators depends on the single-thread performance of the host machine and, as we mentioned before, this is not doubling every two years but every three years and a half. This increasing difference between the complexity of the simulated machine and simulation speed is what we call the simulation speed gap. Because of the simulation speed gap, computer architecture simulators are increasingly slow. The simulation of a reference benchmark may take several weeks or even months. Researchers are concious of this problem and have been proposing techniques to reduce simulation time. These techniques include the use of reduced application input sets, sampled simulation and parallelization. Another technique to reduce simulation time is raising the level of abstraction of the simulated model. In this thesis we advocate for this approach. First, we decide to use trace-driven simulation because it does not require to provide functional simulation, and thus, allows to raise the level of abstraction beyond the instruction-stream representation. However, trace-driven simulation has several limitations, the most important being the inability to reproduce the dynamic behavior of multithreaded applications. In this thesis we propose a simulation methodology that employs a trace-driven simulator together with a runtime sytem that allows the proper simulation of multithreaded applications by reproducing the timing-dependent dynamic behavior at simulation time. Having this methodology, we evaluate the use of multiple levels of abstraction to reduce simulation time, from a high-speed application-level simulation mode to a detailed instruction-level mode. We provide a comprehensive evaluation of the impact in accuracy and simulation speed of these abstraction levels and also show their applicability and usefulness depending on the target evaluations. We also compare these levels of abstraction with the existing ones in popular computer architecture simulators. Also, we validate the highest abstraction level against a real machine. One of the interesting levels of abstraction for the simulation of multi-cores is the memory mode. This simulation mode is able to model the performanceof a superscalar out-of-order core using memory-access traces. At this level of abstraction, previous works have used filtered traces that do not include L1 hits, and allow to simulate only L2 misses for single-core simulations. However, simulating multithreaded applications using filtered traces as in previous works has inherent inaccuracies. We propose a technique to reduce such inaccuracies and evaluate the speed-up, applicability, and usefulness of memory-level simulation. All in all, this thesis contributes to knowledge with techniques for the simulation of chip multiprocessors with hundreds of cores using traces. It states and evaluates the trade-offs of using varying degress of abstraction in terms of accuracy and simulation speed.

  • Performance and Power Optimizations in Chip Multiprocessors for Throughput-Aware Computation  Open access

     Vega, Augusto Javier
    Defense's date: 2013-07-30
    Universitat Politècnica de Catalunya
    Theses

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    El excesivo consumo de potencia de los procesadores actuales ha desacelerado el incremento en la frecuencia operativa de los mismos para dar lugar a la era de los procesadores con múltiples núcleos y múltiples hilos de ejecución. Por ejemplo, el procesador POWER7 de IBM, lanzado al mercado en 2010, incorpora ocho núcleos en el mismo chip, con cuatro hilos de ejecución por núcleo. Esto da lugar a nuevas oportunidades y desafíos para los arquitectos de software y hardware. A nivel de software, las aplicaciones pueden beneficiarse del abundante número de núcleos e hilos de ejecución para aumentar el rendimiento. Pero esto obliga a los programadores a crear aplicaciones altamente paralelas y sistemas operativos capaces de planificar correctamente la ejecución de las mismas. A nivel de hardware, el creciente número de núcleos e hilos de ejecución ejerce presión sobre la interfaz de memoria, ya que el ancho de banda de memoria crece a un ritmo más lento. Además de los problemas de ancho de banda de memoria, el consumo de energía del chip se eleva debido a la dificultad de los fabricantes para reducir suficientemente los voltajes de operación entre generaciones de procesadores. Esta tesis presenta innovaciones para mejorar el ancho de banda y consumo de energía en procesadores multinúcleo en el ámbito de la computación orientada a rendimiento ("throughput-aware computation"): una memoria caché de último nivel ("last-level cache" o LLC) optimizada para ancho de banda, un banco de registros vectorial optimizado para ancho de banda, y una heurística para planificar la ejecución de aplicaciones paralelas orientada a mejorar la eficiencia del consumo de potencia y desempeño.En contraste con los diseños de LLC de última generación, nuestra organización evita la duplicación de datos y, por tanto, no requiere de técnicas de coherencia. El espacio de direcciones de memoria se distribuye estáticamente en la LLC con un entrelazado de grano fino. La ausencia de replicación de datos aumenta la capacidad efectiva de la memoria caché, lo que se traduce en mejores tasas de acierto y mayor ancho de banda en comparación con una LLC coherente. Utilizamos la técnica de "doble buffering" para ocultar la latencia adicional necesaria para acceder a datos remotos.El banco de registros vectorial propuesto se compone de miles de registros y se organiza como una agregación de bancos. Incorporamos a cada banco una pequeña unidad de cómputo de propósito especial ("local computation element" o LCE). Este enfoque ---que llamamos "computación en banco de registros"--- permite superar el número limitado de puertos en el banco de registros. Debido a que cada LCE es una unidad de cómputo con soporte SIMD ("single instruction, multiple data") y todas ellas pueden proceder de forma concurrente, la estrategia de "computación en banco de registros" constituye un dispositivo SIMD altamente paralelo.Por último, presentamos una heurística para planificar la ejecución de aplicaciones paralelas orientada a reducir el consumo de energía del chip, colocando dinámicamente los hilos de ejecución a nivel de software entre los hilos de ejecución a nivel de hardware. La heurística obtiene, en tiempo de ejecución, información de consumo de potencia y desempeño del chip para inferir las características de las aplicaciones. Por ejemplo, si los hilos de ejecución a nivel de software comparten datos significativamente, la heurística puede decidir colocarlos en un menor número de núcleos para favorecer el intercambio de datos entre ellos. En tal caso, los núcleos no utilizados se pueden apagar para ahorrar energía.Cada vez es más difícil encontrar soluciones de arquitectura "a prueba de balas" para resolver las limitaciones de escalabilidad de los procesadores actuales. En consecuencia, creemos que los arquitectos deben atacar dichos problemas desde diferentes flancos simultáneamente, con innovaciones complementarias.

    The so-called "power (or power density) wall" has caused core frequency (and single-thread performance) to slow down, giving rise to the era of multi-core/multi-thread processors. For example, the IBM POWER4 processor, released in 2001, incorporated two single-thread cores into the same chip. In 2010, IBM released the POWER7 processor with eight 4-thread cores in the same chip, for a total capacity of 32 execution contexts. The ever increasing number of cores and threads gives rise to new opportunities and challenges for software and hardware architects. At software level, applications can benefit from the abundant number of execution contexts to boost throughput. But this challenges programmers to create highly-parallel applications and operating systems capable of scheduling them correctly. At hardware level, the increasing core and thread count puts pressure on the memory interface, because memory bandwidth grows at a slower pace ---phenomenon known as the "bandwidth (or memory) wall". In addition to memory bandwidth issues, chip power consumption rises due to manufacturers' difficulty to lower operating voltages sufficiently every processor generation. This thesis presents innovations to improve bandwidth and power consumption in chip multiprocessors (CMPs) for throughput-aware computation: a bandwidth-optimized last-level cache (LLC), a bandwidth-optimized vector register file, and a power/performance-aware thread placement heuristic. In contrast to state-of-the-art LLC designs, our organization avoids data replication and, hence, does not require keeping data coherent. Instead, the address space is statically distributed all over the LLC (in a fine-grained interleaving fashion). The absence of data replication increases the cache effective capacity, which results in better hit rates and higher bandwidth compared to a coherent LLC. We use double buffering to hide the extra access latency due to the lack of data replication. The proposed vector register file is composed of thousands of registers and organized as an aggregation of banks. We leverage such organization to attach small special-function "local computation elements" (LCEs) to each bank. This approach ---referred to as the "processor-in-regfile" (PIR) strategy--- overcomes the limited number of register file ports. Because each LCE is a SIMD computation element and all of them can proceed concurrently, the PIR strategy constitutes a highly-parallel super-wide-SIMD device (ideal for throughput-aware computation). Finally, we present a heuristic to reduce chip power consumption by dynamically placing software (application) threads across hardware (physical) threads. The heuristic gathers chip-level power and performance information at runtime to infer characteristics of the applications being executed. For example, if an application's threads share data, the heuristic may decide to place them in fewer cores to favor inter-thread data sharing and communication. In such case, the number of active cores decreases, which is a good opportunity to switch off the unused cores to save power. It is increasingly harder to find bulletproof (micro-)architectural solutions for the bandwidth and power scalability limitations in CMPs. Consequently, we think that architects should attack those problems from different flanks simultaneously, with complementary innovations. This thesis contributes with a battery of solutions to alleviate those problems in the context of throughput-aware computation: 1) proposing a bandwidth-optimized LLC; 2) proposing a bandwidth-optimized register file organization; and 3) proposing a simple technique to improve power-performance efficiency.

    El excesivo consumo de potencia de los procesadores actuales ha desacelerado el incremento en la frecuencia operativa de los mismos para dar lugar a la era de los procesadores con múltiples núcleos y múltiples hilos de ejecución. Por ejemplo, el procesador POWER7 de IBM, lanzado al mercado en 2010, incorpora ocho núcleos en el mismo chip, con cuatro hilos de ejecución por núcleo. Esto da lugar a nuevas oportunidades y desafíos para los arquitectos de software y hardware. A nivel de software, las aplicaciones pueden beneficiarse del abundante número de núcleos e hilos de ejecución para aumentar el rendimiento. Pero esto obliga a los programadores a crear aplicaciones altamente paralelas y sistemas operativos capaces de planificar correctamente la ejecución de las mismas. A nivel de hardware, el creciente número de núcleos e hilos de ejecución ejerce presión sobre la interfaz de memoria, ya que el ancho de banda de memoria crece a un ritmo más lento. Además de los problemas de ancho de banda de memoria, el consumo de energía del chip se eleva debido a la dificultad de los fabricantes para reducir suficientemente los voltajes de operación entre generaciones de procesadores. Esta tesis presenta innovaciones para mejorar el ancho de banda y consumo de energía en procesadores multinúcleo en el ámbito de la computación orientada a rendimiento ("throughput-aware computation"): una memoria caché de último nivel ("last-level cache" o LLC) optimizada para ancho de banda, un banco de registros vectorial optimizado para ancho de banda, y una heurística para planificar la ejecución de aplicaciones paralelas orientada a mejorar la eficiencia del consumo de potencia y desempeño. En contraste con los diseños de LLC de última generación, nuestra organización evita la duplicación de datos y, por tanto, no requiere de técnicas de coherencia. El espacio de direcciones de memoria se distribuye estáticamente en la LLC con un entrelazado de grano fino. La ausencia de replicación de datos aumenta la capacidad efectiva de la memoria caché, lo que se traduce en mejores tasas de acierto y mayor ancho de banda en comparación con una LLC coherente. Utilizamos la técnica de "doble buffering" para ocultar la latencia adicional necesaria para acceder a datos remotos. El banco de registros vectorial propuesto se compone de miles de registros y se organiza como una agregación de bancos. Incorporamos a cada banco una pequeña unidad de cómputo de propósito especial ("local computation element" o LCE). Este enfoque ---que llamamos "computación en banco de registros"--- permite superar el número limitado de puertos en el banco de registros. Debido a que cada LCE es una unidad de cómputo con soporte SIMD ("single instruction, multiple data") y todas ellas pueden proceder de forma concurrente, la estrategia de "computación en banco de registros" constituye un dispositivo SIMD altamente paralelo. Por último, presentamos una heurística para planificar la ejecución de aplicaciones paralelas orientada a reducir el consumo de energía del chip, colocando dinámicamente los hilos de ejecución a nivel de software entre los hilos de ejecución a nivel de hardware. La heurística obtiene, en tiempo de ejecución, información de consumo de potencia y desempeño del chip para inferir las características de las aplicaciones. Por ejemplo, si los hilos de ejecución a nivel de software comparten datos significativamente, la heurística puede decidir colocarlos en un menor número de núcleos para favorecer el intercambio de datos entre ellos. En tal caso, los núcleos no utilizados se pueden apagar para ahorrar energía. Cada vez es más difícil encontrar soluciones de arquitectura "a prueba de balas" para resolver las limitaciones de escalabilidad de los procesadores actuales. En consecuencia, creemos que los arquitectos deben atacar dichos problemas desde diferentes flancos simultáneamente, con innovaciones complementarias.

  • Evaluating techniques for parallelization tuning in MPI, OmpSs and MPI/OmpSs  Open access

     Subotic, Vladimir
    Defense's date: 2013-07-26
    Universitat Politècnica de Catalunya
    Theses

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    La programación paralela consiste en dividir un problema de computación entre múltiples unidades de procesamiento y definir como interactúan (comunicación y sincronización) para garantizar un resultado correcto. El rendimiento de unprograma paralelo normalmente está muy lejos de ser óptimo: el desequilibrio de la carga computacional y la excesiva interacción entre las unidades de procesamiento a menudo causa ciclos perdidos, reduciendo la eficiencia de la computación paralela.En esta tesis proponemos técnicas orientadas a explotar mejor el paralelismo en aplicaciones paralelas, poniendo énfasis en técnicas que incrementan el asincronismo. En teoría, estas técnicas prometen múltiples beneficios. Primero, tendrían que mitigar el retraso de la comunicación y la sincronización, y por lo tanto incrementar el rendimiento global. Además, la calibración de la paralelización tendría que exponer un paralelismo adicional, incrementando la escalabilidad de la ejecución. Finalmente, un incremente en el asincronismo proveería una tolerancia mayor a redes de comunicación lentas y ruido externo.En la primera parte de la tesis, estudiamos el potencial para la calibración del paralelismo a través de MPI. En concreto, exploramos técnicas automáticas para solapar la comunicación con la computación. Proponemos una técnica demensajería especulativa que incrementa el solapamiento y no requiere cambios en la aplicación MPI original. Nuestra técnica identifica automáticamente la actividad MPI de la aplicación y la reinterpreta usando solicitudes MPI no bloqueantes situadas óptimamente. Demostramos que esta técnica maximiza el solapamiento y, en consecuencia, acelera la ejecución y permite una mayor tolerancia a las reducciones de ancho de banda. Aún así, en el caso de cargas de trabajo científico realistas, mostramos que el potencial de solapamiento está significativamente limitado por el patrón según el cual cada proceso MPI opera localmente en el paso de mensajes.En la segunda parte de esta tesis, exploramos el potencial para calibrar el paralelismo híbrido MPI/OmpSs. Intentamos obtener una comprensión mejor del paralelismo de aplicaciones híbridas MPI/OmpSs para evaluar de qué manera se ejecutarían en futuras máquinas. Exploramos como las aplicaciones MPI/OmpSs pueden escalar en una máquina paralela con centenares de núcleos por nodo. Además, investigamos cómo este paralelismo de cada nodo se reflejaría en las restricciones de la red de comunicación. En especia, nos concentramos en identificar secciones críticas de código en MPI/OmpSs. Hemos concebido una técnica que rápidamente evalúa, para una aplicación MPI/OmpSs dada y la máquina objetivo seleccionada, qué sección de código tendría que ser optimizada para obtener la mayor ganancia de rendimiento.También estudiamos técnicas para explorar rápidamente el paralelismo potencial de OmpSs inherente en las aplicaciones.Proporcionamos mecanismos para evaluar fácilmente el paralelismo potencial de cualquier descomposición en tareas.Además, describimos una aproximación iterativa para buscar una descomposición en tareas que mostrará el suficiente paralelismo en la máquina objetivo dada. Para finalizar, exploramos el potencial para automatizar la aproximación iterativa.En el trabajo expuesto en esta tesis hemos diseñado herramientas que pueden ser útiles para otros investigadores de este campo. La más avanzada es Tareador, una herramienta para ayudar a migrar aplicaciones al modelo de programaciónMPI/OmpSs. Tareador proporciona una interfaz simple para proponer una descomposición del código en tareas OmpSs.Tareador también calcula dinámicamente las dependencias de datos entre las tareas anotadas, y automáticamente estima el potencial de paralelización OmpSs. Por último, Tareador da indicaciones adicionales sobre como completar el proceso de migración a OmpSs. Tareador ya se ha mostrado útil al ser incluido en las clases de programación de la UPC.

    Parallel programming is used to partition a computational problem among multiple processing units and to define how they interact (communicate and synchronize) in order to guarantee the correct result. The performance that is achieved when executing the parallel program on a parallel architecture is usually far from the optimal: computation unbalance and excessive interaction among processing units often cause lost cycles, reducing the efficiency of parallel computation. In this thesis we propose techniques oriented to better exploit parallelism in parallel applications, with emphasis in techniques that increase asynchronism. Theoretically, this type of parallelization tuning promises multiple benefits. First, it should mitigate communication and synchronization delays, thus increasing the overall performance. Furthermore, parallelization tuning should expose additional parallelism and therefore increase the scalability of execution. Finally, increased asynchronism would provide higher tolerance to slower networks and external noise. In the first part of this thesis, we study the potential for tuning MPI parallelism. More specifically, we explore automatic techniques to overlap communication and computation. We propose a speculative messaging technique that increases the overlap and requires no changes of the original MPI application. Our technique automatically identifies the application’s MPI activity and reinterprets that activity using optimally placed non-blocking MPI requests. We demonstrate that this overlapping technique increases the asynchronism of MPI messages, maximizing the overlap, and consequently leading to execution speedup and higher tolerance to bandwidth reduction. However, in the case of realistic scientific workloads, we show that the overlapping potential is significantly limited by the pattern by which each MPI process locally operates on MPI messages. In the second part of this thesis, we study the potential for tuning hybrid MPI/OmpSs parallelism. We try to gain a better understanding of the parallelism of hybrid MPI/OmpSs applications in order to evaluate how these applications would execute on future machines and to predict the execution bottlenecks that are likely to emerge. We explore how MPI/OmpSs applications could scale on the parallel machine with hundreds of cores per node. Furthermore, we investigate how this high parallelism within each node would reflect on the network constraints. We especially focus on identifying critical code sections in MPI/OmpSs. We devised a technique that quickly evaluates, for a given MPI/OmpSs application and the selected target machine, which code section should be optimized in order to gain the highest performance benefits. Also, this thesis studies techniques to quickly explore the potential OmpSs parallelism inherent in applications. We provide mechanisms to easily evaluate potential parallelism of any task decomposition. Furthermore, we describe an iterative trialand-error approach to search for a task decomposition that will expose sufficient parallelism for a given target machine. Finally, we explore potential of automating the iterative approach by capturing the programmers’ experience into an expert system that can autonomously lead the search process. Also, throughout the work on this thesis, we designed development tools that can be useful to other researchers in the field. The most advanced of these tools is Tareador – a tool to help porting MPI applications to MPI/OmpSs programming model. Tareador provides a simple interface to propose some decomposition of a code into OmpSs tasks. Tareador dynamically calculates data dependencies among the annotated tasks, and automatically estimates the potential OmpSs parallelization. Furthermore, Tareador gives additional hints on how to complete the process of porting the application to OmpSs. Tareador already proved itself useful, by being included in the academic classes on parallel programming at UPC.

    La programación paralela consiste en dividir un problema de computación entre múltiples unidades de procesamiento y definir como interactúan (comunicación y sincronización) para garantizar un resultado correcto. El rendimiento de un programa paralelo normalmente está muy lejos de ser óptimo: el desequilibrio de la carga computacional y la excesiva interacción entre las unidades de procesamiento a menudo causa ciclos perdidos, reduciendo la eficiencia de la computación paralela. En esta tesis proponemos técnicas orientadas a explotar mejor el paralelismo en aplicaciones paralelas, poniendo énfasis en técnicas que incrementan el asincronismo. En teoría, estas técnicas prometen múltiples beneficios. Primero, tendrían que mitigar el retraso de la comunicación y la sincronización, y por lo tanto incrementar el rendimiento global. Además, la calibración de la paralelización tendría que exponer un paralelismo adicional, incrementando la escalabilidad de la ejecución. Finalmente, un incremente en el asincronismo proveería una tolerancia mayor a redes de comunicación lentas y ruido externo. En la primera parte de la tesis, estudiamos el potencial para la calibración del paralelismo a través de MPI. En concreto, exploramos técnicas automáticas para solapar la comunicación con la computación. Proponemos una técnica de mensajería especulativa que incrementa el solapamiento y no requiere cambios en la aplicación MPI original. Nuestra técnica identifica automáticamente la actividad MPI de la aplicación y la reinterpreta usando solicitudes MPI no bloqueantes situadas óptimamente. Demostramos que esta técnica maximiza el solapamiento y, en consecuencia, acelera la ejecución y permite una mayor tolerancia a las reducciones de ancho de banda. Aún así, en el caso de cargas de trabajo científico realistas, mostramos que el potencial de solapamiento está significativamente limitado por el patrón según el cual cada proceso MPI opera localmente en el paso de mensajes. En la segunda parte de esta tesis, exploramos el potencial para calibrar el paralelismo híbrido MPI/OmpSs. Intentamos obtener una comprensión mejor del paralelismo de aplicaciones híbridas MPI/OmpSs para evaluar de qué manera se ejecutarían en futuras máquinas. Exploramos como las aplicaciones MPI/OmpSs pueden escalar en una máquina paralela con centenares de núcleos por nodo. Además, investigamos cómo este paralelismo de cada nodo se reflejaría en las restricciones de la red de comunicación. En especia, nos concentramos en identificar secciones críticas de código en MPI/OmpSs. Hemos concebido una técnica que rápidamente evalúa, para una aplicación MPI/OmpSs dada y la máquina objetivo seleccionada, qué sección de código tendría que ser optimizada para obtener la mayor ganancia de rendimiento. También estudiamos técnicas para explorar rápidamente el paralelismo potencial de OmpSs inherente en las aplicaciones. Proporcionamos mecanismos para evaluar fácilmente el paralelismo potencial de cualquier descomposición en tareas. Además, describimos una aproximación iterativa para buscar una descomposición en tareas que mostrará el suficiente paralelismo en la máquina objetivo dada. Para finalizar, exploramos el potencial para automatizar la aproximación iterativa. En el trabajo expuesto en esta tesis hemos diseñado herramientas que pueden ser útiles para otros investigadores de este campo. La más avanzada es Tareador, una herramienta para ayudar a migrar aplicaciones al modelo de programación MPI/OmpSs. Tareador proporciona una interfaz simple para proponer una descomposición del código en tareas OmpSs. Tareador también calcula dinámicamente las dependencias de datos entre las tareas anotadas, y automáticamente estima el potencial de paralelización OmpSs. Por último, Tareador da indicaciones adicionales sobre como completar el proceso de migración a OmpSs. Tareador ya se ha mostrado útil al ser incluido en las clases de programación de la UPC.

  • Access to the full text
    Efficient cache architectures for reliable hybrid voltage operation using EDC codes  Open access

     Maric, Bojan; Abella Ferrer, Jaume; Valero Cortes, Mateo
    Design, Automation and Test in Europe
    Presentation's date: 2013-03
    Presentation of work at congresses

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    Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 ¿) required for new market segments such as body, urban life and environment monitoring. Caches have been shown to be the highest energy and area consumer in those chips. This paper proposes a novel, hybrid-operation (high Vcc, ultra-low Vcc), single-Vcc domain cache architecture based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with Error Detection and Correction (EDC) features for high reliability and performance predictability. Our architecture is proven to largely outperform existing solutions in terms of energy and area.

    Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 p) required for new market segments such as body, urban life and environment monitoring. Caches have been shown to be the highest energy and area consumer in those chips. This paper proposes a novel, hybrid-operation (high Vcc, ultra-low Vcc), single-Vcc domain cache architecture based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with Error Detection and Correction (EDC) features for high reliability and performance predictability. Our architecture is proven to largely outperform existing solutions in terms of energy and area.

    Postprint (author’s final draft)

  • Global misrouting policies in two-level hierarchical networks

     Garcia, Marina; Vallejo, Enrique; Beivide Palacio, Ramon; Odriozola, Miguel; Camarero Coterillo, Cristobal; Valero Cortes, Mateo; Labarta Mancho, Jesus Jose; Rodriguez, German
    International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip
    Presentation's date: 2013-01
    Presentation of work at congresses

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    Dragonfly networks are composed of interconnected groups of routers. Adaptive routing allows packets to be forwarded minimally or non-minimally adapting to the traffic conditions in the network. While minimal routing sends traffic directly between groups, non-minimal routing employs an intermediate group to balance network load. A random selection of this intermediate group (denoted as RRG) typically implies an extra local hop in the source group, what increases average path length and can reduce performance. In this paper we identify different policies for the selection of such intermediate group and explore their performance. Interestingly, simulation results show that an eager policy (denoted as CRG) that selects the intermediate group only between those directly connected to the ongoing router causes starvation in some network nodes. On the contrary, the best performance is obtained by a "mixed mode" policy (denoted as MM) that adds a local hop when the packet has moved away from the source router

    Dragonfly networks are composed of interconnected groups of routers. Adaptive routing allows packets to be forwarded minimally or non-minimally adapting to the traffic conditions in the network. While minimal routing sends traffic directly between groups, non-minimal routing employs an intermediate group to balance network load. A random selection of this intermediate group (denoted as RRG) typically implies an extra local hop in the source group, what increases average path length and can reduce performance. In this paper we identify different policies for the selection of such intermediate group and explore their performance. Interestingly, simulation results show that an eager policy (denoted as CRG) that selects the intermediate group only between those directly connected to the ongoing router causes starvation in some network nodes. On the contrary, the best performance is obtained by a by a \mixed mode" policy (denoted as MM) that adds a local hop when the packet has moved away from the source router.

  • Identifying critical code sections in dataflow programming models

     Subotic, Vladimir; Sancho, Jose Carlos; Labarta Mancho, Jesus Jose; Valero Cortes, Mateo
    Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
    Presentation of work at congresses

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    The years of practice in optimizing applications point that the major issue is focus - identifying the critical code section whose optimization would yield the highest overall speedup. While this issue is mainly solved for sequential applications, it remains a serious hurdle in the world of parallel computing. Furthermore, the newest dataflow parallel programming models expose very irregular parallelism, making the identification of the critical code section even harder. To address this issue, we designed an environment that identifies critical code sections in applications. The programmer can use this environment to estimate the potential benefits of the optimization for a specific parallel platform. This is very important because the programmer can anticipate the benefits of his optimization and assure that the optimization is worth the effort. Furthermore, we showed that in many applications, the choice of the critical code section decisively depends on the configuration of the target machine. For instance, in HP Linpack, optimizing a task that takes 0.49% of the total computation time yields the overall speedup of less than 0.25% on one machine, and at the same time, yields the overall speedup of more than 24% on a machine with different number of cores.

    The years of practice in optimizing applications point that the major issue is focus - identifying the critical code section whose optimization would yield the highest overall speedup. While this issue is mainly solved for sequential applications, it remains a serious hurdle in the world of parallel computing. Furthermore, the newest dataflow parallel programming models expose very irregular parallelism, making the identification of the critical code section even harder. To address this issue, we designed an environment that identifies critical code sections in applications. The programmer can use this environment to estimate the potential benefits of the optimization for a specific parallel platform. This is very important because the programmer can anticipate the benefits of his optimization and assure that the optimization is worth the effort. Furthermore, we showed that in many applications, the choice of the critical code section decisively depends on the configuration of the target machine. For instance, in HP Linpack, optimizing a task that takes 0.49% of the total computation time yields the overall speedup of less than 0.25% on one machine, and at the same time, yields the overall speedup of more than 24% on a machine with different number of cores.

  • APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation

     Maric, Bojan; Abella Ferrer, Jaume; Valero Cortes, Mateo
    Design Automation Conference
    Presentation of work at congresses

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    Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown to be the main energy and area consumer in those chips. This paper proposes simple, hybrid-operation (high Vcc, ultra-low Vcc), single-Vcc domain Adaptive Performance- Predictable Low-Energy (APPLE) L1 cache designs based on replacing energy-hungry SRAM cells by more energy-efficient and smaller cells enhanced with extra cache lines set up in an adapted victim cache to still enable strong performance guarantees. APPLE caches are proven to largely outperform existing solutions in terms of energy and area efficiency.

    Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown to be the main energy and area consumer in those chips. This paper proposes simple, hybrid-operation (high Vcc, ultra-low Vcc), single-Vcc domain Adaptive Performance- Predictable Low-Energy (APPLE) L1 cache designs based on replacing energy-hungry SRAM cells by more energy-efficient and smaller cells enhanced with extra cache lines set up in an adapted victim cache to still enable strong performance guarantees. APPLE caches are proven to largely outperform existing solutions in terms of energy and area efficiency.

  • The problem of evaluating CPU-GPU systems with 3d visualization applications

     Verdu Mula, Javier; Pajuelo González, Manuel Alejandro; Valero Cortes, Mateo
    IEEE micro
    Date of publication: 2012-12
    Journal article

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    Complex, computationally demanding 3D visualization applications can be used as benchmarks to evaluate CPU-GPU systems. However, because those applications are time dependent, their execution is not deterministic. Thus, measurements can vary from one execution to another. This article proposes a methodology that enforces the starting times of frames so that applications behave deterministically.

    Complex, computationally demanding 3D visualization applications can be used as benchmarks to evaluate CPU-GPU systems. However, because those applications are time dependent, their execution is not deterministic. Thus, measurements can vary from one execution to another. This article proposes a methodology that enforces the starting times of frames so that applications behave deterministically.

  • Profiling and optimizing transactional memory applications

     Stipic, Srdjan; Zyulkyarov, Ferad Hasanov; Harris, Tim; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Hur, Ibrahim; Valero Cortes, Mateo
    International journal of parallel programming
    Date of publication: 2012-02
    Journal article

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  • Dynamic tolerance region computing for multimedia

     Alvarez Martinez, Carlos; Corbal San Adrian, Jesus; Valero Cortes, Mateo
    IEEE transactions on computers
    Date of publication: 2012
    Journal article

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  • Parallel job scheduling for power constrained HPC systems

     Etinski, Maja; Corbalan Gonzalez, Julita; Labarta Mancho, Jesus Jose; Valero Cortes, Mateo
    Parallel computing
    Date of publication: 2012-12
    Journal article

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  • Circuit design of a dual-versioning L1 data cache

     Seyedi, Azam; Armejach, Adrià; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Hur, Ibrahim; Valero Cortes, Mateo
    Integration. The VLSI journal
    Date of publication: 2012-06
    Journal article

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  • Understanding the future of energy-performance trade-off via DVFS in HPC environments

     Etinski, Maja; Corbalan Gonzalez, Julita; Labarta Mancho, Jesus Jose; Valero Cortes, Mateo
    Journal of parallel and distributed computing
    Date of publication: 2012-04
    Journal article

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  • CPU accounting for multicore processors

     Ruiz Luque, Jose Carlos; Moreto Planas, Miquel; Cazorla, Francisco J.; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortes, Mateo
    IEEE transactions on computers
    Date of publication: 2012-02
    Journal article

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  • Resource-bounded multicore emulation using Beefarm

     Arcas Abella, Oriol; Sonmez, N.; Sayilar, G.; Singh, S.; Unsal, Osman Sabri; Cristal Kestelman, Adrian; Hur, Ibrahim; Valero Cortes, Mateo
    Microprocessors and microsystems
    Date of publication: 2012-11
    Journal article

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    In this article, we present the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years both in FPGA and computer architecture communities. We explain how we modify and extend a MIPS-based open-source soft core, we discuss various design tradeoffs to make efficient use of the bounded resources available on chip and we demonstrate superior scalability compared to traditional software instruction set simulators through experimental results running Software Transactional Memory (STM) benchmarks. Based on our experience, we comment on the pros and cons and the future trends of using hardware-based emulation for multicore research.

  • Hardware transactional memory with software-defined conflicts

     Titos Gil, Ruben; Acacio, Manuel E.; García Carrasco, José M.; Harris, Tim; Cristal Kestelman, Adrian; Unsal, Osman Sabri; Hur, Ibrahim; Valero Cortes, Mateo
    ACM transactions on architecture and code optimization
    Date of publication: 2012-01
    Journal article

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    In this paper we investigate the benefits of turning the concept of transactional conflict from its traditionally fixed definition into a variable one that can be dynamically controlled in software. We propose the extension of the atomic language construct with an attribute that specifies the definition of conflict, so that programmers can write code which adjusts what kinds of conflicts are to be detected, relaxing or tightening the conditions according to the forms of interference that can be tolerated by a particular algorithm. Using this performance-motivated construct, specific conflict information can be associated with portions of code, as each transaction is provided with a local definition that applies while it executes. We find that defining conflicts in software makes possible the removal of dependencies which arise as a result of the coarse synchronization style encouraged by the TM programming model. We illustrate the use of the proposed construct in a variety of use cases with real applications, showing how programmers can take advantage of their knowledge about the problem and other global information not available at run-time. We describe how to implement a hardware TM design that utilizes this software construct. Our experiments reveal that leveraging software-defined conflicts, the programmer is able to achieve significant reductions in the number of aborts--over 50% for most applications. At 16 threads, our system with software-defined conflicts outperforms LogTM-SE in nearly all benchmarks, reaching an average reduction in execution time of 18%.

  • On the simulation of large-scale architectures using multiple application abstraction levels

     Rico Carro, Alejandro; Cabarcas Jaramillo, Felipe; Villavieja Prados, Carlos; Pavlovic, Milan; Vega, Augusto; Etsion, Yoav; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    ACM transactions on architecture and code optimization
    Date of publication: 2012-01-23
    Journal article

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    Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not suitable for simulating large-scale architectures, nor are theymeant for this. Moreover,microarchitecture design decisions are irrelevant, or even misleading, for early processor design stages and high-level explorations. This allows one to raise the abstraction level of the simulated architecture, and also the application abstraction level, as it does not necessarily have to be represented as an instruction stream. In this paper we introduce a definition of different application abstraction levels, and how these are employed in TaskSim, a multi-core architecture simulator, to provide several architecture modeling abstractions, and simulate large-scale architectures with hundreds of cores. We compare the simulation speed of these abstraction levels to the ones in existing simulation tools, and also evaluate their utility and accuracy. Our simulations show that a very high-level abstraction, which may be even faster than native execution, is useful for scalability studies on parallel applications; and that just simulating explicit memory transfers, we achieve accurate simulations for architectures using non-coherent scratchpad memories, with just a 25xslowdown compared to native execution. Furthermore, we revisit trace memory simulation techniques, that are more abstract than instruction-by-instruction simulations and provide an 18x simulation speedup.

  • Doctor Honoris Causa en Informàtica

     Valero Cortes, Mateo
    Award or recognition

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  • Advanced Grant European Research Council (convocatòria 2012)

     Valero Cortes, Mateo
    Award or recognition

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  • Vector extensions for decision support DBMS acceleration

     Hayes, Timothy; Palomar Perez, Oscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortes, Mateo
    IEEE/ACM International Symposium on Microarchitecture
    Presentation's date: 2012-12-04
    Presentation of work at congresses

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    Database management systems (DBMS) have become an essential tool for industry and research and are often a significant component of data centres. As a result of this criticality, efficient execution of DBMS engines has become an important area of investigation. This work takes a top-down approach to accelerating decision support systems (DSS) on x86-64 microprocessors using vector ISA exten- sions. In the first step, a leading DSS DBMS is analysed for potential data-level parallelism. We discuss why the existing multimedia SIMD extensions (SSE/AVX) are not suitable for capturing this parallelism and propose a complementary instruction set reminiscent of classical vector architectures. The instruction set is implemented using unin- trusive modifications to a modern x86-64 microarchitecture tailored for DSS DBMS. The ISA and microarchitecture are evaluated using a cycle-accurate x86-64 microarchitectural simulator coupled with a highly-detailed memory simulator. We have found a single oper- ator is responsible for 41% of total execution time for the TPC-H DSS benchmark. Our results show performance speedups between 1.94x and 4.56x for an implementation of this operator run with our proposed hardware modifications.

  • HIPEAC 3 - European Network of Excellence on HighPerformance Embedded Architecture and Compilers

     Navarro Mas, Nacho; Gil Gómez, Maria Luisa; Martorell Bofill, Xavier; Valero Cortes, Mateo; Ayguade Parra, Eduard; Ramirez Bellido, Alejandro; Badia Sala, Rosa Maria; Labarta Mancho, Jesus Jose; Llaberia Griño, Jose M.
    Participation in a competitive project

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  • Optimal task assignment in multithreaded processors: a statistical approach

     Cakarevic, Vladimir; Radojkovic, Petar; Moreto Planas, Miquel; Verdu Mula, Javier; Pajuelo González, Manuel Alejandro; Cazorla, Francisco J.; Nemirovsky, Mario; Valero Cortes, Mateo
    International Conference on Architectural Support for Programming Languages and Operating Systems
    Presentation's date: 2012
    Presentation of work at congresses

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    The introduction of massively multithreaded (MMT) processors, comprised of a large number of cores with many shared resources, has made task scheduling, in particular task to hardware thread assignment, one of the most promising ways to improve system performance. However, finding an optimal task assignment for a workload running on MMT processors is an NP-complete problem. Due to the fact that the performance of the best possible task assignment is unknown, the room for improvement of current task-assignment algorithms cannot be determined. This is a major problem for the industry because it could lead to: (1)~A waste of resources if excessive effort is devoted to improving a task assignment algorithm that already provides a performance that is close to the optimal one, or (2)~significant performance loss if insufficient effort is devoted to improving poorly-performing task assignment algorithms. In this paper, we present a method based on Extreme Value Theory that allows the prediction of the performance of the optimal task assignment in MMT processors. We further show that executing a sample of several hundred or several thousand random task assignments is enough to obtain, with very high confidence, an assignment with a performance that is close to the optimal one. We validate our method with an industrial case study for a set of multithreaded network applications running on an UltraSPARC~T2 processor.

  • The Multi-State Processors

     Gonzalez Martin, Isidro
    Defense's date: 2012-10-26
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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  • Improving cache management policies using dynamic reuse distances

     Duong, Nam; Zhao, Dali; Kim, Taesu; Cammarota, Rosario; Valero Cortes, Mateo; Veidenbaum, Alexander V
    IEEE/ACM International Symposium on Microarchitecture
    Presentation's date: 2012-12
    Presentation of work at congresses

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    Cache management policies such as replacement, bypass, or shared cache partitioning have been relying on data reuse behavior to predict the future. This paper proposes a new way to use dynamic reuse distances to further improve such policies. A new replacement policy is proposed which prevents replacing a cache line until a certain number of accesses to its cache set, called a Protecting Distance (PD). The policy protects a cache line long enough for it to be reused, but not beyond that to avoid cache pollution. This can be combined with a bypass mechanism that also relies on dynamic reuse analysis to bypass lines with less expected reuse. A miss fetch is bypassed if there are no unprotected lines. A hit rate model based on dynamic reuse history is proposed and the PD that maximizes the hit rate is dynamically computed. The PD is recomputed periodically to track a program's memory access behavior and phases...

  • ADAM : an efficient data management mechanism for hybrid high and ultra-low voltage operation caches

     Maric, Bojan; Abella Ferrer, Jaume; Valero Cortes, Mateo
    ACM Great Lakes Symposium on VLSI
    Presentation's date: 2012
    Presentation of work at congresses

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    Semiconductor technology evolution enables the design of ultra-low-cost chips (e.g., below 1 USD) required for new market segments such as environment, urban life and body monitoring, etc. Recently, hybrid-operation (high Vcc, ultra-low Vcc) single-Vcc-domain cache designs have been proposed to tackle the needs of those chips. However, existing data management policies are far from being optimal during high Vcc operation. This paper presents ADAM, a new and extremely simple Adaptive Data Management mechanism, which is tailored to detect hit distribution and changing application conditions dynamically at ne grain with negligible hardware overhead. ADAM is proven to save signi cant energy (29% on average) in L1 caches with negligible performance degradation (1.7% on average), thus improving the energy-delay product (EDP) noticeably across di erent cache con gurations with respect to all existing data management approaches.

  • Dynamic cache partitioning based on the MLP of cache misses

     Moreto Planas, Miquel; Cazorla, Francisco J.; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    Lecture notes in computer science
    Date of publication: 2011
    Journal article

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  • Scalable multicore architectures for long DNA sequence comparison

     Sanchez Castaño, Friman; Cabarcas Jaramillo, Felipe; Ramirez Bellido, Alejandro; Valero Cortes, Mateo
    Concurrency and computation. Practice and experience
    Date of publication: 2011-12-10
    Journal article

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  • The International Exascale Software Project roadmap

     Dongarra, Jack J.; Beckman, Pete; Moore, Terry; Aerts, Patrick; Aloisio, Giovanni; Andre, Jean-Claude; Barkai, David; Berthou, Jean-Yves; Boku, Taisuke; Braunschweig, Bertrand; Cappello, Franck; Chapman, Barbara M.; Chi, Xuebin; Choudhary, Alok N.; Dosanjh, Sudip S.; Dunning, Thom H.; Fiore, Sandro; Geist, Al; Gropp, Bill; Harrison, Robert J.; Hereld, Mark; Heroux, Michael A.; Hoisie, Adolfy; Hotta, Koh; Jin, Zhong; Ishikawa, Yutaka; Johnson, Fred; Kale, Sanjay; Kenway, Richard; Keyes, David E.; Kramer, Bill; Labarta Mancho, Jesus Jose; Lichnewsky, Alain; Lippert, Thomas; Lucas, Bob; Maccabe, Barney; Matsuoka, Satoshi; Messina, Paul; Michielse, Peter; Mohr, Bernd; Müller, Matthias S; Nagel, Wolfgang E.; Nakashima, Hiroshi; Papka, Michael E.; Reed, Daniel A.; Sato, Mitsuhisa; Seidel, Edward; Shalf, John; Skinner, David; Snir, Marc; Sterling, Thomas L.; Stevens, Rick; Streitz, Fred; Sugar, Bob; Sumimoto, Shinji; Tang, William; Taylor, John; Thakur, Rajeev; Trefethen, Anne E.; Valero Cortes, Mateo; van der Steen, Aad; Vetter, Jeffrey S.; Williams, Peg; Wisniewski, Robert W.; Yelick, Katherine A.
    International journal of high performance computing applications
    Date of publication: 2011-02
    Journal article

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    Over the last 20 years, the open-source community has provided more and more software on which the worldâ¿¿s high-performance computing systems depend for performance and productivity. The community has invested millions of dollars and years of effort to build key components. However, although the investments in these separate software elements have been tremendously valuable, a great deal of productivity has also been lost because of the lack of planning, coordination, and key integration of technologies necessary to make them work together smoothly and efficiently, both within individual petascale systems and between different systems. It seems clear that this completely uncoordinated development model will not provide the software needed to support the unprecedented parallelism required for peta/ exascale computation on millions of cores, or the flexibility required to exploit new hardware models and features, such as transactional memory, speculative execution, and graphics processing units. This report describes the work of the community to prepare for the challenges of exascale computing, ultimately combing their efforts in a coordinated International Exascale Software Project.

  • Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems

     Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortes, Mateo
    ACM SIGBED Review
    Date of publication: 2011-09
    Journal article

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    Power demand grows much faster than battery capacity in embedded systems. Dynamic voltage and frequency scaling (DVFS) has been shown to be extremely efficient to save energy due to the exponential dependence of power on voltage. However, voltage/frequency cannot be blindly scaled in hard real-time systems because DVFS techniques impact on the execution time, and so potentially on the worst-case execution time (WCET) of tasks. This paper presents a new DVFS technique for hard real-time systems that measures dynamically the intra-task slack existing between the actual execution time of a task and its WCET estimation, and exploits it to perform DVFS guaranteeing that the WCET is not affected. Concretely, our approach exploits the slack available due to contention in the use of shared resources in a multi-core system.

  • Characterizing power and temperature behavior of POWER6-Based System

     Jiménez, Victor; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Valero Cortes, Mateo; Boneti, Carlos; Kursun, Eren; Cher, Chen-Yong; Isci, Canturk; Buyuktosunoglu, Alper; Bose, Pradip
    IEEE Journal of emerging and selected topics in power electronics
    Date of publication: 2011-09
    Journal article

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    Microprocessor architectures have become increasingly power limited in recent years. Currently power and thermal envelopes dictate peak performance limits more than any other design constraint. In this work, we characterize thermal behavior and power consumption of an IBM POWER6-based system. We perform the characterization at several levels: application, operating system, and hardware level, both when the system is idle, and under load. At hardware level, we report a 25% reduction in total system power consumption by using the processor low power mode. We also study the effect of the hardware thread prioritization mechanism provided by POWER6 on different workloads and how this mechanism can be used to limit power consumption. From this static characterization study we derive a model based on performance counters that allows us to predict the total power consumption of the POWER6 system with an average error under 3% for CMP and 5% for SMT. To the best of our knowledge, this is the first power model of a system including CMP+SMT processors. The work reported in this paper can be generalized to model power consumption for a broader class of systems. Such power modeling is required for studying promising power reduction techniques. In terms of dynamic methods, intelligent thread placement can result in a boost in power efficiency. Our results show that such a power-aware thread placement results in up to 5 × improvement in energy-delay squared product for our POWER6 system.

  • CASTELL: A HETEROGENEOUS CMP ARCHITECTURE SCALABLE TO HUNDREDS OF PROCESSORS  Open access

     Cabarcas Jaramillo, Felipe
    Defense's date: 2011-09-19
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    Technology improvements and power constrains have taken multicore architectures to dominate microprocessor designs over uniprocessors. At the same time, accelerator based architectures have shown that heterogeneous multicores are very efficient and can provide high throughput for parallel applications, but with a high-programming effort. We propose Castell a scalable chip multiprocessor architecture that can be programmed as uniprocessors, and provides the high throughput of accelerator-based architectures. Castell relies on task-based programming models that simplify software development. These models use a runtime system that dynamically finds, schedules, and adds hardware-specific features to parallel tasks. One of these features is DMA transfers to overlap computation and data movement, which is known as double buffering. This feature allows applications on Castell to tolerate large memory latencies and lets us design the memory system focusing on memory bandwidth. In addition to provide programmability and the design of the memory system, we have used a hierarchical NoC and added a synchronization module. The NoC design distributes memory traffic efficiently to allow the architecture to scale. The synchronization module is a consequence of the large performance degradation of application for large synchronization latencies. Castell is mainly an architecture framework that enables the definition of domain-specific implementations, fine-tuned to a particular problem or application. So far, Castell has been successfully used to propose heterogeneous multicore architectures for scientific kernels, video decoding (using H.264), and protein sequence alignment (using Smith-Waterman and clustalW). It has also been used to explore a number of architecture optimizations such as enhanced DMA controllers, and architecture support for task-based programming models. iii

  • PARALLEL VIDEO DECODING  Open access

     Alvarez Mesa, Mauricio
    Defense's date: 2011-09-08
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    Digital video is a popular technology used in many different applications. The quality of video, expressed in the spatial and temporal resolution, has been increasing continuously in the last years. In order to reduce the bitrate required for its storage and transmission, a new generation of video encoders and decoders (codecs) have been developed. The latest video codec standard, known as H.264/AVC, includes sophisticated compression tools that require more computing resources than any previous video codec. The combination of high quality video and the advanced compression tools found in H.264/AVC has resulted in a significant increase in the computational requirements of video decoding applications. The main objective of this thesis is to provide the performance required for real-time operation of high quality video decoding using programmable architectures. Our solution has been the simultaneous exploitation of multiple levels of parallelism. On the one hand, video decoders have been modified in order to extract as much parallelism as possible. And, on the other hand, general purpose architectures has been enhanced for exploiting the type of parallelism that is present in video codec applications.

    El vídeo digital es una tecnología popular utilizada en una gran variedad de aplicaciones. La calidad de vídeo, expresada en la resolución espacial y temporal, ha ido aumentando constantemente en los últimos años. Con el fin de reducir la tasa de bits requerida para su almacenamiento y transmisión, se ha desarrollado una nueva generación de codificadores y decodificadores (códecs) de vídeo. El códec estándar de vídeo más reciente, conocido como H.264/AVC, incluye herramientas sofisticadas de compresión que requieren más recursos de computación que los códecs de vídeo anteriores. El efecto combinado del vídeo de alta calidad y las herramientas de compresión avanzada incluidas en el H.264/AVC han llevado a un aumento significativo de los requerimientos computacionales de la decodificación de vídeo. El objetivo principal de esta tesis es proporcionar el rendimiento necesario para la decodificación en tiempo real de vídeo de alta calidad. Nuestra solución ha sido la explotación simultánea de múltiples niveles de paralelismo. Por un lado, se realizaron modificaciones en el decodificador de vídeo con el fin de extraer múltiples niveles de paralelismo. Y, por otro lado, se modificaron las arquitecturas de propósito general para mejorar la explotación del tipo paralelismo que está presente en las aplicaciones de vídeo. Primero hicimos un análisis de la escalabilidad de dos extensiones de Instrucción Simple con Múltiples Datos (SIMD por sus siglas en inglés): una de una dimensión (1D) y otra matricial de dos dimensiones (2D). Se demostró que al escalar la extensión 2D se obtiene un mayor rendimiento con una menor complejidad que al escalar la extensión 1D. Luego se realizó una caracterización de la decodificación de H.264/AVC en aplicaciones de alta definición (HD) donde se identificaron los núcleos principales. Debido a la falta de un punto de referencia (benchmark) adecuado para la decodificación de vídeo HD, desarrollamos uno propio, llamado HD-VideoBench el cual incluye aplicaciones completas de codificación y decodificación de vídeo junto con una serie de secuencias de vídeo en HD. Después optimizamos los núcleos más importantes del decodificador H.264/AVC usando instrucciones SIMD. Sin embargo, los resultados no alcanzaron el máximo rendimiento posible debido al efecto negativo de la desalineación de los datos en memoria. Como solución, evaluamos el hardware y el software necesarios para realizar accesos no alineados. Este soporte produjo mejoras significativas de rendimiento en la aplicación. Aparte se realizó una investigación sobre cómo extraer paralelismo de nivel de tarea. Se encontró que ninguno de los mecanismos existentes podía escalar para sistemas masivamente paralelos. Como alternativa, desarrollamos un nuevo algoritmo que fue capaz de encontrar miles de tareas independientes al explotar paralelismo de nivel de macrobloque. Luego implementamos una versión paralela del decodificador de H.264 en una máquina de memoria compartida distribuida (DSM por sus siglas en inglés). Sin embargo esta implementación no alcanzó el máximo rendimiento posible debido al impacto negativo de las operaciones de sincronización y al efecto del núcleo de decodificación de entropía. Con el fin de eliminar estos cuellos de botella se evaluó la paralelización al nivel de imagen de la fase de decodificación de entropía combinada con la paralelización al nivel de macrobloque de los demás núcleos. La sobrecarga de las operaciones de sincronización se eliminó casi por completo mediante el uso de operaciones aceleradas por hardware. Con todas las mejoras presentadas se permitió la decodificación, en tiempo real, de vídeo de alta definición y alta tasa de imágenes por segundo. Como resultado global se creó una solución escalable capaz de usar el número creciente procesadores en las arquitecturas multinúcleo.

  • Programming, Debugging, Profiling and Optimizing Transactional Memory Programs  Open access

     Hasanov Zyulkyarov, Ferad
    Defense's date: 2011-07-19
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    Transactional memory (TM) is a new optimistic synchronization technique which has the potential of making shared memory parallel programming easier compared to locks without giving up from the performance. This thesis explores four aspects in the research of transactional memory. First, it studies how programming with TM compares to locks. During the course of work, it develops the first real transactional application ¿ AtomicQuake. AtomicQuake is adapted from the parallel version of the Quake game server by replacing all lock-based synchronization with atomic blocks. Findings suggest that programming with TM is indeed easier than locks. However the performance of current software TM systems falls behind the efficiently implemented lock-based versions of the same program. Also, the same findings report that the proposed language level extensions are not sufficient for developing robust production level software and that the existing development tools such as compilers, debuggers, and profilers lack support for developing transactional application. Second, this thesis introduces new set of debugging principles and abstractions. These new debugging principles and abstractions enable debugging synchronization errors which manifest at coarse atomic block level, wrong code inside atomic blocks, and also performance errors related to the implementation of the atomic block. The new debugging principles distinguish between debugging at the language level constructs such as atomic blocks and debugging the atomic blocks based on how they are implemented whether TM or lock inference. These ideas are demonstrated by implementing a debugger extension for WinDbg and the ahead-of-time C# to X86 Bartok-STM compiler. Third, this thesis investigates the type of performance bottlenecks in TM applications and introduces new profiling techniques to find and understand these bottlenecks. The new profiling techniques provide in-depth and comprehensive information about the wasted work caused by aborting transactions. The individual profiling abstractions can be grouped in three groups: (i) techniques to identify multiple conflicts from a single program run, (ii) techniques to describe the data structures involved in conflicts by using a symbolic path through the heap, rather than a machine address, and (iii) visualization techniques to summarize which transactions conflict most. The ideas were demonstrated by building a lightweight profiling framework for Bartok-STM and an offline tool which process and display the profiling data. Forth, this thesis explores and introduces new TM specific optimizations which target the wasted work due to aborting transactions. Using the results obtained with the profiling tool it analyzes and optimizes several applications from the STAMP benchmark suite. The profiling techniques effectively revealed TM-specific bottlenecks such as false conflicts and contentions accesses to data structures. The discovered bottlenecks were subsequently eliminated with using the new optimization techniques. Among the optimization highlights are the transaction checkpoints which reduced the wasted work in Intruder with 40%, decomposing objects to eliminate false conflicts in Bayes, early release in Labyrinth which decreased wasted work from 98% to 1%, using less contentions data structures such as chained hashtable in Intruder and Genome which have higher degree of parallelism.

  • Simulating whole supercomputer applications

     González Garcia, Juan; Casas, Marc; Gimenez Lucas, Judit; Moreto Planas, Miquel; Ramirez Bellido, Alejandro; Labarta Mancho, Jesus Jose; Valero Cortes, Mateo
    IEEE micro
    Date of publication: 2011-06
    Journal article

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    Detailed simulations of large scale message-passing interface parallel applications are extremely time consuming and resource intensive. A new methodology that combines signal processing and data mining techniques plus a multilevel simulation reduces the simulated data by various orders of magnitude. This reduction makes possible detailed software performance analysis and accurate performance predictions in a reasonable time.

  • Assessing accelerator-based HPC reverse time migration

     Araya Polo, Mauricio; Cabezas, Javier; Hanzich, Mauricio; Pericas, Miquel; Rubio, Fèlix; Gelado Fernandez, Isaac; Shafiq, Muhammad; Morancho Llena, Enrique; Navarro Mas, Nacho; Ayguade Parra, Eduard; Cela Espin, Jose M.; Valero Cortes, Mateo
    IEEE transactions on parallel and distributed systems
    Date of publication: 2011-01
    Journal article

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  • Hybrid transactional memory with pessimistic concurrency control

     Vallejo, Enrique; Sanyal, Sutirtha; Harris, Tim; Vallejo, Fernando; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortes, Mateo; Beivide Palacio, Julio Ramon
    International journal of parallel programming
    Date of publication: 2011-06
    Journal article

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    Transactional Memory (TM) intends to simplify the design and implementation of the shared-memory data structures used in parallel software. Many Software TM systems are based on writer-locks to protect the data being modified. Such implementations can suffer from the “privatization” problem, in which transactional and non-transactional accesses to the same location can lead to inconsistent results. One solution is the use of Pessimistic Concurrency Control, but it entails an important performance penalty due to the need of reader-writer locking. In this paper a hybrid TM design is proposed to reduce the performance overheads caused by the use of these locks while combining three desirable features: i) full TM functionality whether or not the architectural support is present; ii) execution of a single common code path in software or hardware; and, iii) immunity from the privatization problem. The analysis shows how a Hybrid TM can lose important properties, such as starvation freedom. To overcome this issue, Directory Reservations is presented, a low-cost mechanism improving existent solutions designed for Hardware TM.