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  • Introducció als computadors (A): col·lecció de problemes

     Navarro Guerrero, Juan Jose; Muntés Mulero, Víctor; Cruz Diaz, Josep-llorenç; Palomar Perez, Oscar; Sanchez Castaño, Friman; Solé Simó, Marc
    Date of publication: 2011-02
    Book

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  • Introducció als computadors (A): pràctiques

     Navarro Guerrero, Juan Jose
    Date of publication: 2011-02
    Book

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  • Reusing cached schedules in an out-of-order processor with in-order issue logic  Open access

     Palomar Perez, Oscar
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    Modern processors use out-of-order processing logic to achieve high performance in Instructions Per Cycle (IPC) but this logic has a serious impact on the achievable frequency. In order to get better performance out of smaller transistors there is a trend to increase the number of cores per die instead of making the cores themselves bigger. Moreover, for throughput-oriented and server workloads, simpler in-order processors that allow more cores per die and higher design frequencies are becoming the preferred choice. Unfortunately, for other workloads this type of cores result in a lower single thread performance. There are many workloads where it is still important to achieve good single thread performance. In this thesis we present the ReLaSch processor. Its aim is to enable high IPC cores capable of running at high clock frequencies by processing the instructions using simple superscalar in-order issue logic and caching instruction groups that are dynamically scheduled in hardware after commit, that is, out of the critical path and only when really needed. Objective This thesis has several research goals: • Show that the dynamic scheduler of a conventional out-of-order processor does a lot of redundant work because it ignores the repetitiveness of code. • Propose a complete superscalar out-of-order architecture that reduces the amount of redundant work done by creating the schedules once in dedicated hardware, storing them in a cache of schedules and reusing the schedules as much as possible. • Place the scheduler out of the critical path of execution, which should be enabled by the reduction of work that it must do. Thus, the execution path of our proposed processor can be simpler than that of a conventional out-of-order processor. Proposal and results We present the \textbf{ReLaSch} processor, named after Reused Late Schedules, in which the creation of issue-groups is removed from the critical path of execution and uses a simple and small in-order issue logic. It just wakes-up and selects the instructions of a single issue-group each cycle, instead of processing the instructions of a whole issue queue. A new logic at the end of the conventional pipeline schedules the committed instructions. The new scheduler can be complex since it is not in the critical path of execution. The schedules are cached and whenever it is possible an rgroup is read and its instructions executed. The schedules are reused, lowering the pressure on the scheduling logic. In some cases, the ReLaSch processor is able to outperform a conventional out-of-order processor, because the post-commit scheduler has a broader vision of the code. For instance, while ReLaSch can schedule together two independent instructions that are distant in the code, a conventional out-oforder processor only issues them in the same cycle if both are in-flight. The ReLaSch processor predicts the branch targets, memory aliases and latencies at scheduling time, out of the critical path. The prediction is based on the most recent executions at scheduling time. Furthermore, most of the register renaming process is performed by the scheduler and is removed from the execution pipeline. Our experiments show that ReLaSch has the same average IPC as our reference out-of-order processor and is clearly better than the reference inorder processor (1.55 speed-up). In all cases it outperforms the in-order processor and in 23 benchmarks out of 40 it has a higher IPC than the reference out-of-order processor.

  • Una colección de metáforas para explicar (y entender) el EEES  Open access

     Valero Garcia, Miguel; Navarro Guerrero, Juan Jose
    Jornadas de Enseñanza Universitaria de la Informática
    p. 1-8
    Presentation's date: 2010-07-08
    Presentation of work at congresses

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    La implantación del sistema europeo de créditos dentro del marco del Espacio Europeo de Educación Superior tiene implicaciones profundas en nuestra labor como profesores al pasar de una docencia centrada en la enseñanza (en el profesor) a otra centrada en el aprendizaje (en el estudiante). Con frecuencia, estas implicaciones no son bien explicadas o comprendidas. En este artículo se propone un conjunto amplio de metáforas que pueden resultar útiles para explicar y comprender mejor dichas implicaciones, con una nota de humor y con una mirada fresca y diferente al problema, que nos ayude a tomar un poco de distancia con nuestras circunstancias particulares y prejuicios.

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    Niveles de competencia de los objetivos formativos en las ingenierías  Open access

     Valero Garcia, Miguel; Navarro Guerrero, Juan Jose
    Jornadas de Enseñanza Universitaria de la Informática
    p. 1-6
    Presentation's date: 2010-07-17
    Presentation of work at congresses

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    En este artículo se discute la cuestión del nivel de competencia de los objetivos formativos en nuestras materias, y las implicaciones en los métodos docentes y de evaluación. A partir de esta discusión se ofrecen algunas reflexiones críticas sobre la situación actual de la docencia en nuestro contexto.

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    Competencias profesionales para el Grado en Ingeniería Informática  Open access

     Sanchez Carracedo, Fermin; Sancho Samsó, Maria Ribera; Botella Lopez, Pere; Garcia Almiñana, Jordi; Aluja Banet, Tomas; Navarro Guerrero, Juan Jose; Balcazar Navarro, Jose Luis
    Date of publication: 2009
    Book chapter

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    Degrees in the EHEA (European Higher Education Area) must be designed based on professional skills, so that when the students finish their studies they become competent professionals in the labour market. In this paper we propose a weighted list of skills for a undergraduate degree in Informatics Engineering, classified into two groups: technical and generic. Technical skills are divided into five different itineraries:computer engineering, computer science, information systems, information technologies and software engineering. Los planes de Estudios del EEES (Espacio Europeo de Educación Superior) deben ser diseñados a partir de competencias profesionales, de forma que al final de sus estudios el egresado se convierta en un profesional competente en el mercado laboral. En este artículo se propone una lista de competencias ponderada para un título de Grado en Ingeniería Informática clasificadas en dos grupos: transversales y técnicas. Dentro de las técnicas se definen cinco itinerarios distintos: computación, ingeniería de computadores, ingeniería del software, sistemas de información y tecnologías de la Información.

  • ARQUITECTURA DE COMPUTADORS D'ALTRES PRESTACIONS (CAP)

     Jimenez Castells, Marta; Pericas Gleim, Miquel; Navarro Guerrero, Juan Jose; Llaberia Griño, Jose M.; Llosa Espuny, Jose Francisco; Villavieja Prados, Carlos; Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Ramirez Bellido, Alejandro; Morancho Llena, Enrique; Fernandez Jimenez, Agustin; Pajuelo González, Manuel Alejandro; Olive Duran, Angel; Sanchez Carracedo, Fermin; Moreto Planas, Miquel; Verdu Mula, Javier; Abella Ferrer, Jaume; Valero Cortes, Mateo
    Competitive project

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  • Laboratorio de Introducción a los Computadores: funcionamiento y dificultades docentes

     Navarro Guerrero, Juan Jose; Cruz Diaz, Josep-llorenç; Faúndez Zanuy, Marcos; Gonzalez Tallada, Marc; Manso Cortes, Oscar; Muntés Mulero, Víctor; Palomar Perez, Oscar; Rodero Castro, Ivan; Sanchez Castaño, Friman; Solé Simó, Marc
    Jornades de Docència del Departament d'Arquitectura de Computadors
    p. 1-20
    Presentation's date: 2009-02
    Presentation of work at congresses

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    Reusing cached schedules in an out-of-order processor with in-order issue logic  Open access

     Palomar Perez, Oscar; Juan, Toni; Navarro Guerrero, Juan Jose
    IEEE International Conference on Computer Design: VLSI in Computers and Processors
    p. 246-253
    DOI: 10.1109/ICCD.2009.5413146
    Presentation's date: 2009-10-06
    Presentation of work at congresses

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    The complex and powerful out-of-order issue logic dismisses the repetitive nature of the code, unlike what caches or branch predictors do. We show that 90% of the cycles, the group of instructions selected by the issue logic belongs to just 13% of the total different groups issued: the issue logic of an out-of-order processor is constantly re-discovering what it has already found. To benefit from the repetitive nature of instruction issue, we move the scheduling logic after the commit stage, out of the critical path of execution. The schedules created there are cached and reused to feed a simple in-order issue logic, that could result in a higher frequency design. We present the complete design of our ReLaSch processor, that achieves the same average IPC than a conventional out-of-order processor, and a 1.56 speed-up over the IPC of an in-order processor. We actually surpass the out-of-order IPC in 23 out of 40 SPEC benchmarks, mainly because the broader vision of the code after the commit stage allows creating better schedules.

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    Diez metáforas para entender (y explicar) el nuevo modelo docente para el EEES  Open access

     Valero Garcia, Miguel; Navarro Guerrero, Juan Jose
    @TIC
    num. 1, p. 3-8
    Date of publication: 2008-10
    Journal article

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    La adopción de los nuevos modelos docentes, centrados en el aprendizaje del alumno, tal y como se nos requiere en el marco del Espacio Europeo de Educación Superior, tiene implicaciones profundas en nuestra labor como profesores. Con frecuencia, estas implicaciones no son bien explicadas o comprendidas. En este artículo se proponen 10 metáforas que pueden resultar útiles para explicar y comprender mejor dichas implicaciones, con una nota de humor y con una mirada fresca y diferente al problema, que nos ayude a tomar un poco de distancia con nuestras circunstancias particulares y prejuicios.

  • Hypermatrix oriented supernode amalgamation

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Journal of supercomputing
    Vol. 46, num. 1, p. 84-104
    DOI: 10.1007/s11227-008-0188-y
    Date of publication: 2008-10
    Journal article

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    FAQ sobre la adaptación de asignaturas al EEES: docencia centrada en el aprendizaje del estudiante  Open access

     Valero Garcia, Miguel; Navarro Guerrero, Juan Jose
    ReVisión
    Vol. 1, num. 2, p. 23-38
    Date of publication: 2008
    Journal article

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    Muchas son las preguntas y las dudas que se plantean los profesores a la hora de adaptar una asignatura al Espacio Europeo de Educación Superior. Pasar de un modelo de docencia centrado en la enseñanza (en el profesor) a un modelo centrado en el aprendizaje (en el estudiante) plantea diferentes tipos de preguntas, que suelen repetirse en todos los foros de discusión. Algunas de estas preguntas tienen que ver con los nuevos métodos docentes (en qué se basan, qué ventajas aportan, cómo se implementan…). Otras tienen que ver con la dificultad de implantar los nuevos enfoques en el contexto actual de nuestra universidad, con los estudiantes que nos llegan y con los profesores que tenemos. En este documento respondemos a 23 de estas preguntas típicas, agrupadas en los dos apartados comentados, con la esperanza de que las respuestas ayuden a los profesores a adaptar sus asignaturas al nuevo entorno.

  • Aspectos organizativos que dificultan o facilitan la adaptación al EEES de asignaturas con varios profesores y grupos de clase

     Valero Garcia, Miguel; Navarro Guerrero, Juan Jose
    Jornadas de Enseñanza Universitaria de la Informática
    p. 27-34
    Presentation of work at congresses

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  • Aspectos organizativos que dificultan o facilitan la adaptación al EEES de asignaturas con varios profesores y grupos de clase

     Navarro Guerrero, Juan Jose
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2008-07-09
    Presentation of work at congresses

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  • Competencias profesionales del Grado en Ingeniería Informática

     Sanchez Carracedo, Fermin; Sancho Samsó, Maria Ribera; Botella Lopez, Pere; Balcazar Navarro, Jose Luis; Garcia Almiñana, Jordi; Navarro Guerrero, Juan Jose; Aluja Banet, Tomas
    Jornadas de Enseñanza Universitaria de la Informática
    p. 123-130
    Presentation's date: 2008-07-09
    Presentation of work at congresses

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  • Competencias profesionales del Grado en Ingenieria Informatica

     Navarro Guerrero, Juan Jose
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2008-07-09
    Presentation of work at congresses

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    Algunas preguntas frecuentes y nuestras respuestas favoritas sobre la pertinencia de los métodos docentes centrados en el estudiante para adaptar una asignatura al EEES  Open access

     Valero Garcia, Miguel; Navarro Guerrero, Juan Jose
    Novática: revista de la Asociación de Técnicos de Informática
    num. 192, p. 48-50
    Date of publication: 2008
    Journal article

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    Muchas son las cuestiones y las dudas que se plantean los profesores a la hora de adaptar una asignatura al Espacio Europeo de Educación Superior. Pasar de un modelo de docencia centrado en la enseñanza a un modelo centrado en el aprendizaje plantea diferentes tipos de preguntas, que suelen repetirse en todos los foros de discusión. En este artículo respondemos a tres preguntas habituales sobre la pertinencia de los cambios metodológicos (¿Es este enfoque realmente mejor?), que son las preguntas que uno se plantea antes de empezar a caminar. Las preguntas están relacionadas con: 1) la planificación detallada de actividades dentro y fuera de clase y si esto reduce la iniciativa y autonomía de los futuros graduados, 2) los métodos de evaluación en los que pierde relevancia el examen final y si esto conlleva una reducción del nivel de exigencia de la asignatura y 3) el uso de tiempo de clase para realizar actividades destinadas a adquirir nuevas habilidades transversales y el peligro de que esto conlleve una reducción del los contenidos técnicos de la asignatura.

  • La planificación del trabajo del estudiante y el desarrollo de su autonomía en el aprendizaje basado en proyectos

     Valero Garcia, Miguel; Navarro Guerrero, Juan Jose
    Date of publication: 2008-12-15
    Book chapter

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  • Niveles de competencia y evaluación continua en Introducción a los Computadores

     Navarro Guerrero, Juan Jose; Solé Simó, Marc; Palomar Perez, Oscar; Cruz Diaz, Josep-llorenç; Muntés Mulero, Víctor; Sanchez Castaño, Friman; Martorell Bofill, Xavier
    Jornades de Docència del Departament d'Arquitectura de Computadors
    p. 1-11
    Presentation's date: 2008-02
    Presentation of work at congresses

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  • Analysis of a sparse hypermatrix Cholesky with fixed-sized blocking

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Applicable algebra in engineering communication and computing
    Vol. 18, num. 3, p. 279-295
    Date of publication: 2007-05
    Journal article

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  • Exploiting computer resources for fast nearest neighbor classification

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Pattern analysis and applications
    Vol. 10, num. 4, p. 265-275
    Date of publication: 2007-10
    Journal article

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  • Sparse Hypermatrix Cholesky: Customization for High Performance

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    IAENG international journal of applied mathematics
    Vol. 36, num. 1, p. 6-12
    Date of publication: 2007-02
    Journal article

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  • Introducción a los Computadores: una asignatura en el EEES

     Navarro Guerrero, Juan Jose; Cruz Diaz, Josep-llorenç; Muntés Mulero, Víctor; Palomar Perez, Oscar; Sanchez Castaño, Friman; Solé Simó, Marc
    Jornades de Docència del Departament d'Arquitectura de Computadors
    p. 1-16
    Presentation's date: 2007-02
    Presentation of work at congresses

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  • L'assignatura Introducció als Computadors

     Navarro Guerrero, Juan Jose
    Jornades de Docència del Departament d'Arquitectura de Computadors. 10 Anys de Jornades
    p. 1-10
    Presentation of work at congresses

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  • Definición de objetivos docentes: experiencias de uso

     Navarro Guerrero, Juan Jose
    Jornades de Docència del Departament d'Arquitectura de Computadors. 10 Anys de Jornades
    p. 1-10
    Presentation of work at congresses

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  • FAQs sobre la adaptacion de las asignaturas al EEES

     Valero Garcia, Miguel; Navarro Guerrero, Juan Jose
    Jornadas de Enseñanza Universitaria de la Informática
    p. 96-104
    Presentation of work at congresses

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  • Guía para la redacción de los objetivos de una asignatura

     Navarro Guerrero, Juan Jose; Tubella Murgadas, Jordi; Valero Garcia, Miguel; Sanchez Carracedo, Fermin
    Jornades de Docència del Departament d'Arquitectura de Computadors. 10 Anys de Jornades
    p. 1-10
    Presentation's date: 2007-02
    Presentation of work at congresses

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  • El doctorat del DAC

     Gonzalez Colas, Antonio Maria; Ayguade Parra, Eduard; Espasa Sans, Roger; Garcia Vidal, Jorge; Navarro Guerrero, Juan Jose
    Jornades de Docència del Departament d'Arquitectura de Computadors. 10 Anys de Jornades
    p. 1-10
    Presentation of work at congresses

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  • Aprendizaje activo

     Barcelò Ordinas, José María; Cortes Rossello, Antonio; Fernandez Jimenez, Agustin; Garcia Vidal, Jorge; Morancho Llena, Enrique; Navarro Guerrero, Juan Jose; Valero Garcia, Miguel; Valero-Garcia, Miguel
    Jornades de Docència del Departament d'Arquitectura de Computadors. 10 Anys de Jornades
    p. 1-10
    Presentation of work at congresses

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  • Cómo rellenar las plantillas de las asignaturas que pide la FIB

     Navarro Guerrero, Juan Jose; Garcia Vidal, Jorge
    Jornades de Docència del Departament d'Arquitectura de Computadors. 10 Anys de Jornades
    p. 1-10
    Presentation of work at congresses

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  • L'experiència docent a la fase de selecció de les carreres de la FIB: Introducció als Computadors

     Navarro Guerrero, Juan Jose
    Jornades de Docència del Departament d'Arquitectura de Computadors. 10 Anys de Jornades
    p. 1-10
    Presentation of work at congresses

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  • FAQ sobre la docencia centrada en el aprendizaje

     Valero Garcia, Miguel; Navarro Guerrero, Juan Jose
    Date of publication: 2007-11-30
    Book chapter

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  • Compiler-Optimized Kernels: An Efficient Alternative to Hand-Coded Inner Kernels

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Lecture notes in computer science
    Vol. 1, num. 3984, p. 762-771
    Date of publication: 2006-05
    Journal article

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  • Optimization of a Statically Partitioned Hypermatrix Sparse Cholesky Factorization

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Lecture notes in computer science
    Vol. 3732, p. 798-807
    Date of publication: 2006-01
    Journal article

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  • Using Non-canonical Array Layouts in Dense Matrix Operations

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Lecture notes in computer science
    Vol. 4699, num. 1, p. 580-588
    Date of publication: 2006-06
    Journal article

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  • A Framework for Accurate Measurements with Low Resolution Clocks

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    The 18th IASTED International Conference on Software Engineering and Applications
    p. 228-232
    Presentation of work at congresses

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  • A Framework for Accurate Measurements with Low Resolution Clocks

     Navarro Guerrero, Juan Jose
    The 18th IASTED International Conference on Software Engineering and Applications
    Presentation's date: 2006-11-13
    Presentation of work at congresses

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  • Using nonlinear array layouts in dense matrix operation

     Navarro Guerrero, Juan Jose
    Workshop on state-of-the-art in scientific computing (PARA'2006)
    Presentation's date: 2006-06-18
    Presentation of work at congresses

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  • Sparse Hypermatrix Cholesky: Customization for High Performance

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    International Multiconference of Engineers and Computer Scientists 2006
    p. 821-827
    Presentation of work at congresses

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  • Using non-canonical array layouts in dense matrix operation

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Workshop on state-of-the-art in scientific computing (PARA'2006)
    p. 1
    Presentation of work at congresses

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  • Compiler-Optimized Kernels: An Efficient Alternative to Hand-Coded Inner Kernels

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    The 2006 International Conference on Computational Science and its Applications
    p. 762-771
    Presentation of work at congresses

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  • Advances in Sparse Hypermatrix Cholesky Factorization

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Recent Advances in Engineering and Computer Science 2007
    p. 7-24
    Presentation of work at congresses

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  • A framework for efficient execution of matrix computations  Open access

     Herrero Zaragoza, José Ramón
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    Matrix computations lie at the heart of most scientific computational tasks. The solution of linear systems of equations is a very frequent operation in many fields in science, engineering, surveying, physics and others. Other matrix operations occur frequently in many other fields such as pattern recognition and classification, or multimedia applications. Therefore, it is important to perform matrix operations efficiently. The work in this thesis focuses on the efficient execution on commodity processors of matrix operations which arise frequently in different fields.We study some important operations which appear in the solution of real world problems: some sparse and dense linear algebra codes and a classification algorithm. In particular, we focus our attention on the efficient execution of the following operations: sparse Cholesky factorization; dense matrix multiplication; dense Cholesky factorization; and Nearest Neighbor Classification.A lot of research has been conducted on the efficient parallelization of numerical algorithms. However, the efficiency of a parallel algorithm depends ultimately on the performance obtained from the computations performed on each node. The work presented in this thesis focuses on the sequential execution on a single processor.There exists a number of data structures for sparse computations which can be used in order to avoid the storage of and computation on zero elements. We work with a hierarchical data structure known as hypermatrix. A matrix is subdivided recursively an arbitrary number of times. Several pointer matrices are used to store the location ofsubmatrices at each level. The last level consists of data submatrices which are dealt with as dense submatrices. When the block size of this dense submatrices is small, the number of zeros can be greatly reduced. However, the performance obtained from BLAS3 routines drops heavily. Consequently, there is a trade-off in the size of data submatrices used for a sparse Cholesky factorization with the hypermatrix scheme. Our goal is that of reducing the overhead introduced by the unnecessary operation on zeros when a hypermatrix data structure is used to produce a sparse Cholesky factorization. In this work we study several techniques for reducing such overhead in order to obtain high performance.One of our goals is the creation of codes which work efficiently on different platforms when operating on dense matrices. To obtain high performance, the resources offered by the CPU must be properly utilized. At the same time, the memory hierarchy must be exploited to tolerate increasing memory latencies. To achieve the former, we produce inner kernels which use the CPU very efficiently. To achieve the latter, we investigate nonlinear data layouts. Such data formats can contribute to the effective use of the memory system.The use of highly optimized inner kernels is of paramount importance for obtaining efficient numerical algorithms. Often, such kernels are created by hand. However, we want to create efficient inner kernels for a variety of processors using a general approach and avoiding hand-made codification in assembly language. In this work, we present an alternative way to produce efficient kernels automatically, based on a set of simple codes written in a high level language, which can be parameterized at compilation time. The advantage of our method lies in the ability to generate very efficient inner kernels by means of a good compiler. Working on regular codes for small matrices most of the compilers we used in different platforms were creating very efficient inner kernels for matrix multiplication. Using the resulting kernels we have been able to produce high performance sparse and dense linear algebra codes on a variety of platforms.In this work we also show that techniques used in linear algebra codes can be useful in other fields. We present the work we have done in the optimization of the Nearest Neighbor classification focusing on the speed of the classification process.Tuning several codes for different problems and machines can become a heavy and unbearable task. For this reason we have developed an environment for development and automatic benchmarking of codes which is presented in this thesis.As a practical result of this work, we have been able to create efficient codes for several matrix operations on a variety of platforms. Our codes are highly competitive with other state-of-art codes for some problems.

  • Compiler-Optimized Kernels: An Efficient Alternative to Hand-Coded Inner Kernels

     Navarro Guerrero, Juan Jose
    The 2006 International Conference on Computational Science and its Applications
    Presentation's date: 2006-05-07
    Presentation of work at congresses

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  • Adapting Linear Algebra Codes to the Memory Hierarchy Using a Hypermatrix Schem

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Lecture notes in computer science
    p. 1058-1065
    Date of publication: 2005-09
    Journal article

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  • Proccedings of the 4th International Conference on Computer Recognition Systems

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Advances in soft computing
    Vol. 1, p. 1-903
    Date of publication: 2005-05
    Journal article

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  • A Study on Load Imbalance in Parallel Hypermatrix Multiplication Using OpenMP

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    Lecture notes in computer science
    p. 124-131
    Date of publication: 2005-09
    Journal article

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  • Parallel Mutant Reverse Sorting

     Jimenez Gonzalez, Daniel; Navarro Guerrero, Juan Jose; Larriba Pey, Josep
    Date: 2005-07
    Report

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  • Efficient Implementation of Nearest Neighbor Classification

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    4th International Conference on Computer Recognition Systems
    p. 177-186
    Presentation of work at congresses

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  • Intra-Block Amalgamation in Sparse Hypermatrix Cholesky

     Herrero Zaragoza, José Ramón; Navarro Guerrero, Juan Jose
    International Conference on Parallel Processing
    p. 341-349
    Presentation of work at congresses

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