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  • A boolean rule-based approach for manufacturability-aware cell routing

     Cortadella Fortuny, Jordi; Petit Silvestre, Jordi; Gomez Fernandez, Sergio; Moll Echeto, Francesc de Borja
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2014-03-01
    Journal article

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    An approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core contribution is a detailed-routing algorithm based on a Boolean formulation of the problem. The algorithm uses a novel encoding scheme, graph theory to support floating terminals, efficient heuristics to reduce the computational cost, and minimization of the number of unconnected pins in case the cell is unroutable. The versatility of the algorithm is demonstrated by routing single-and double-height cells. The efficiency is ascertained by synthesizing a library with 127 cells in about one hour and a half of CPU time. The layouts derived by the implemented tool have also been compared with the ones from a commercial library; thus, showing the competitiveness of the approach for gridded geometries.

  • Brownian circuits: fundamentals

     Peper, Ferdinand; Lee, Jia; Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Morita, Kenichi
    ACM journal on emerging technologies in computing systems
    Date of publication: 2013-02
    Journal article

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    Random fluctuations will be a major factor interfering with the operation of nanometer scale electronic devices. This article presents circuit architectures that can exploit such fluctuations, if signals have a particlelike (discrete, token-based) character. We define an abstract circuit primitive that, though lacking functionality when used with fluctuation-free signals, becomes universal when fluctuations are allowed. Key to the power of a signal's fluctuations is the ability to explore the state space of a circuit. This ability is used to resolve deadlock situations, which could otherwise only be averted by increased design complexity. The results in this article suggest that in the design of future computers, signal fluctuations, rather than being an impediment to be avoided at any cost, may be an important ingredient to achieve efficient operation

  • Architectural exploration of large-scale hierarchical chip multiprocessors

     Nikitin, Nikita; De San Pedro Martín, Javier; Cortadella Fortuny, Jordi
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2013
    Journal article

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    The continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more hierarchical structures to better exploit locality. To efficiently discover promising architectures within the rapidly growing search space, exhaustive exploration is replaced with tools that implement intelligent search strategies. Moreover, faster analytical models are preferred to costly simulations for estimating the performance and power of CMP architectures. The memory traffic generated by CMP cores has a cyclic dependency with the latency of the memory subsystem, which critically affects the overall system performance. Based on this observation, a novel scalable analytical method is proposed to estimate the performance of highly parallel CMPs (hundreds or thousands of cores) with hierarchical interconnect networks. The method can use customizable probabilistic models and solves the cyclic dependencies between traffic and latency by using a fixed-point strategy. By using the analytical model as a performance and power estimator, an efficient metaheuristic-based search is proposed for the exploration of large design spaces. The proposed techniques are shown to be very accurate and a promising strategy when compared to the results obtained by simulation

    The continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more hierarchical structures to better exploit locality. To efficiently discover promising architectures within the rapidly growing search space, exhaustive exploration is replaced with tools that implement intelligent search strategies. Moreover, faster analytical models are preferred to costly simulations for estimating the performance and power of CMP architectures. The memory traffic generated by CMP cores has a cyclic dependency with the latency of the memory subsystem, which critically affects the overall system performance. Based on this observation, a novel scalable analytical method is proposed to estimate the performance of highly parallel CMPs (hundreds or thousands of cores) with hierarchical interconnect networks. The method can use customizable probabilistic models and solves the cyclic dependencies between traffic and latency by using a fixed-point strategy. By using the analytical model as a performance and power estimator, an efficient metaheuristic-based search is proposed for the exploration of large design spaces. The proposed techniques are shown to be very accurate and a promising strategy when compared to the results obtained by simulation.

  • Area-optimal transistor folding for 1-D gridded cell design

     Cortadella Fortuny, Jordi
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2013-11
    Journal article

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    The 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which consists of breaking large transistors into smaller ones (legs) that can be placed in the active area of the cell. In the 1-D style, diffusion sharing between differently sized transistors is not allowed, thus implying a significant area overhead when active areas with different sizes are required. This paper presents a new formulation of the transistor folding problem in the context of 1-D design style and a mathematical model that delivers area-optimal solutions. The mathematical model can be customized for different variants of the problem, considering flexible transistor sizes and multiple-height cells. An innovative feature of the method is that area optimality can be guaranteed without calculating the actual location of the transistors. The model can also be enhanced to deliver solutions with good routability properties.

  • Membre de l'Academia Europaea

     Cortadella Fortuny, Jordi
    Award or recognition

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  • Automatic Synthesis and Optimization of Chip Multiprocessors  Open access

     Nikitin, Nikita
    Defense's date: 2013-04-05
    Universitat Politècnica de Catalunya
    Theses

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    NikitinLa tecnología de microprocesadores ha experimentado un crecimiento importante durante las últimas décadas. La rápida miniaturización de la tecnología CMOS ha causado un incremento de las frecuencias de operación y del rendimiento por unidad de área, enfrentándose al problema fundamental de disipación de energía. Los Multiprocesadores en Chip (CMPs) se han convertido en el último paradigma para mejorar la eficiencia de consumo y rendimiento de los sistemas de computación, aprovechando el paralelismo inherente en las aplicaciones. Los prototipos y las implementaciones industriales han demostrado los beneficios obtenidos por los CMPs con cientos de núcleos.Los diseñadores de CMPs se enfrentan a numerosas y complicadas decisiones. Algunas de ellas son:- ¿Cuál debería ser el ratio entre el área de los núcleos y el área de la memoria en un chip?- ¿Qué arquitectura de núcleo se debería seleccionar?- ¿Cuántos niveles de jerarquía debería tener el subsistema de memoria?- ¿Qué topologías de interconexión proporcionan una comunicación eficiente en chip?Éstos y muchos otros aspectos crean un espacio complejo multidimensional para la exploración de la arquitectura. Las herramientas para la automatización del diseño empiezan a ser esenciales para hacer factible la exploración de arquitectura, dadas las restricciones del tiempo de comercialización. Los métodos de exploración deben ser eficientes y escalables para aplicarse a las futuras arquitecturas en chip con cientos o miles de núcleos.Una vez fabricados, los CMPs necesitan estrategias para la maximizar su rendimiento. Se necesitan métodos inteligentes para la asignación y planificación de tareas para garantizar el uso total de los beneficios de los procesadores con muchos núcleos. Estos métodos deben tener en cuenta las particularidades de las arquitecturas modernas, como las técnicas avanzadas para ahorro de consumo y las jerarquías complejas de memoria.Esta tesis tiene distintos objetivos. El primero es proponer métodos para el modelado analítico eficiente y la exploración de la arquitectura de CMPs. La eficiencia se consigue mediante el uso de modelos analíticos en lugar de simulaciones, y la sustitución de la exploración exhaustiva con una estrategia de búsqueda inteligente. Además, estos métodos incorporan modelos de alto nivel para la planificación física. Las contribuciones relacionadas están descritas en los Capítulos 3, 4 y 5 del documento.El segundo objetivo de este trabajo es proponer un algoritmo escalable para la asignación de tareas para los CMPs de propósito general con técnicas de control de consumo, para la utilización eficiente de los sistemas de muchos núcleos. Esta contribución se detalla en el Capítulo 6 de la tesis.Finalmente, el tercer objetivo de esta tesis es considerar los aspectos del diseño y la exploración de las interconexiones en chip, y desarrollar un modelo para optimizar conjuntamente el encaminamiento de mensajes y la asignación de canales en las redes de inteconexión. La metodología desarrollada puede ser aplicada a varias clases de sistemas en chip, desde los procesadores de propósito general hasta los sistemas para aplicaciones específicas. El Capítulo 7 describe el modelo propuesto.Los métodos presentados han sido comprobados metódicamente mediante experimentos, cuyos resultados están descritos en esta tesis. Al final del documento se proponen unas posibles direcciones para trabajo futuro.

    The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental issue of power dissipation. Chip Multiprocessors (CMPs) have become the latest paradigm to improve the power-performance efficiency of computing systems by exploiting the parallelism inherent in applications. Industrial and prototype implementations have already demonstrated the benefits achieved by CMPs with hundreds of cores.CMP architects are challenged to take many complex design decisions. Only a few of them are:- What should be the ratio between the core and cache areas on a chip?- Which core architectures to select?- How many cache levels should the memory subsystem have?- Which interconnect topologies provide efficient on-chip communication?These and many other aspects create a complex multidimensional space for architectural exploration. Design Automation tools become essential to make the architectural exploration feasible under the hard time-to-market constraints. The exploration methods have to be efficient and scalable to handle future generation on-chip architectures with hundreds or thousands of cores.Furthermore, once a CMP has been fabricated, the need for efficient deployment of the many-core processor arises. Intelligent techniques for task mapping and scheduling onto CMPs are necessary to guarantee the full usage of the benefits brought by the many-core technology. These techniques have to consider the peculiarities of the modern architectures, such as availability of enhanced power saving techniques and presence of complex memory hierarchies.This thesis has several objectives. The first objective is to elaborate the methods for efficient analytical modeling and architectural design space exploration of CMPs. The efficiency is achieved by using analytical models instead of simulation, and replacing the exhaustive exploration with an intelligent search strategy. Additionally, these methods incorporate high-level models for physical planning. The related contributions are described in Chapters 3, 4 and 5 of the document.The second objective of this work is to propose a scalable task mapping algorithm onto general-purpose CMPs with power management techniques, for efficient deployment of many-core systems. This contribution is explained in Chapter 6 of this document.Finally, the third objective of this thesis is to address the issues of the on-chip interconnect design and exploration, by developing a model for simultaneous topology customization and deadlock-free routing in Networks-on-Chip. The developed methodology can be applied to various classes of the on-chip systems, ranging from general-purpose chip multiprocessors to application-specific solutions. Chapter 7 describes the proposed model.The presented methods have been thoroughly tested experimentally and the results are described in this dissertation. At the end of the document several possible directions for the future research are proposed.

  • Physical planning for the architectural exploration of large-scale chip multiprocessors

     De San Pedro Martín, Javier; Nikitin, Nikita; Cortadella Fortuny, Jordi; Petit Silvestre, Jordi
    IEEE/ACM International Symposium on Networks-on-Chip
    Presentation's date: 2013
    Presentation of work at congresses

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    This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout constraints that enforce regularity in the interconnect networks. Routing is performed on top of memories and components that underutilize the available metal layers for interconnectivity. The experiments demonstrate the impact of physical parameters in the selection of the most efficient architectures. Thus, the integrated flow contributes to deliver physically-viable architectures and simplify the complex design closure of large-scale CMPs.

    This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout constraints that enforce regularity in the interconnect networks. Routing is performed on top of memories and components that underutilize the available metal layers for interconnectivity. The experiments demonstrate the impact of physical parameters in the selection of the most efficient architectures. Thus, the integrated flow contributes to deliver physically-viable architectures and simplify the complex design closure of large-scale CMPs.

  • Physical-aware system-level design for tiled hierarchical chip multiprocessors

     Cortadella Fortuny, Jordi; De San Pedro Martín, Javier; Nikitin, Nikita; Petit Silvestre, Jordi
    ACM International Symposium on Physical Design
    Presentation's date: 2013
    Presentation of work at congresses

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    Tiled hierarchical architectures for Chip Multiprocessors (CMPs) represent a rapid way of building scalable and power-efficient many-core computing systems. At the early stages of the design of a CMP, physical parameters are often ignored and postponed for later design stages. In this work, the importance of physical-aware system-level exploration is investigated, and a strategy for deriving chip floorplans is described. Additionally, wire planning of the on-chip interconnect is performed, as its topology and organization affect the physical layout of the system. Traditional algorithms for floorplanning and wire planning are customized to include physical constraints specific for tiled hierarchical architectures. Over-the-cell routing is used as one of the major area savings strategy. The combination of architectural exploration and physical planning is studied with an example and the impact of the physical aspects on the selection of architectural parameters is evaluated.

  • Static task mapping for tiled chip multiprocessors with multiple voltage islands

     Nikitin, Nikita; Cortadella Fortuny, Jordi
    International Conference on Architecture of Computing Systems
    Presentation's date: 2012-03
    Presentation of work at congresses

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    The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping onto general-purpose CMPs with multiple pre-defined voltage islands for power management. The CMPs are assumed to contain different classes of processing elements with multiple voltage/frequency execution modes to better cover a large range of applications. Task mapping is performed with awareness of both on-chip and off-chip memory traffic, and communication constraints such as the link and memory bandwidth. A novel mapping approach based on Extremal Optimization is proposed for large-scale CMPs. This new combinatorial optimization method has delivered very good results in quality and computational cost when compared to the classical simulated annealing.

  • Analytical performance modeling of hierarchical interconnect fabrics

     Nikitin, Nikita; De San Pedro Martín, Javier; Carmona Vargas, Jose; Cortadella Fortuny, Jordi
    IEEE/ACM International Symposium on Networks-on-Chip
    Presentation's date: 2012
    Presentation of work at congresses

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  • Integrating formal verification in an online judge for e-Learning logic circuit design

     De San Pedro Martín, Javier; Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Petit Silvestre, Jordi
    ACM Technical Symposium on Computer Science Education
    Presentation's date: 2012
    Presentation of work at congresses

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  • Automatic Pipelining of Elastic Systems

     Galceran Oms, Marc
    Defense's date: 2011-09-26
    Department of Computer Science, Universitat Politècnica de Catalunya
    Theses

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  • A scheduling strategy for synchronous elastic designs

     Carmona Vargas, Jose; Julvez, Jorge; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    Fundamenta informaticae
    Date of publication: 2011
    Journal article

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  • Microarchitectural Transformations Using Elasticity

     Galceran Oms, Marc; Gotmanov, Alexander; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    ACM journal on emerging technologies in computing systems
    Date of publication: 2011-12
    Journal article

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  • Access to the full text
    Measuring the tolerance of self-adaptive clocks to supply voltage noise  Open access

     Perez Puigdemont, Jordi; Moll Echeto, Francesc de Borja; Cortadella Fortuny, Jordi
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2011-11-18
    Presentation of work at congresses

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    Simultaneous switching noise has become an important issue due to its signal integrity and timing implications. Therefore a lot of time and resources are spent during the PDN design to minimize the supply voltage variation. This paper presents the self-adaptive clock as an alternative to tolerate the critical path delay variation due to supply noise thanks to its self-adaptable nature. A self-adaptive clock generation circuit is proposed in this paper and its benefits, in terms of clock period reduction, are assessed under a realistic supply noise obtained through simulation for different switching activities.

  • New Region-Based Algorithms for Deriving Bounded Petri Nets

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    IEEE transactions on computers
    Date of publication: 2010-01-26
    Journal article

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  • PERFOMANCE OPTIMIZATION OF ELASTIC SYSTEMS

     DMITRY, BUFISTOV
    Defense's date: 2010-12-01
    Department of Computer Science, Universitat Politècnica de Catalunya
    Theses

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  • TOWARDS THE AUTOMATIC SYNTHESIS OF ASYNCHRONOUS COMMUNICATION MECHANISMS

     Costa Gorgônio, Kyller
    Defense's date: 2010-12-01
    Department of Computer Science, Universitat Politècnica de Catalunya
    Theses

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  • On the Performance Evaluation of Multi-Guarded Marked Graphs with Single-Server Semantics

     Julvez Bueno, Jorge Emilio; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    Discrete event dynamic systems-theory and applications
    Date of publication: 2010-09
    Journal article

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  • Introduction to programming

     Cortadella Fortuny, Jordi; Gavaldà Mestre, Ricard; Orejas Valdes, Fernando
    Date: 2010-09-01
    Report

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  • A Recursive Paradigm to Solve Boolean Relations

     Baneres, D; Cortadella Fortuny, Jordi; Kishinevsky, M
    IEEE transactions on computers
    Date of publication: 2009-04
    Journal article

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  • Guest Editorial: Special Section on Asynchronous Circuits and Systems

     Cortadella Fortuny, Jordi; Taubin, A
    IEEE transactions on very large scale integration (VLSI) systems
    Date of publication: 2009-07
    Journal article

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  • Elastic Circuits

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Kishinevsky, M; Taubin, A
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2009-10
    Journal article

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  • A recursive approach for Process Mining

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi
    Date: 2009-02
    Report

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  • Region-based Algorithms for Process Mining and Synthesis of Petri Nets

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi
    Date: 2009-02
    Report

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  • Genet: a Tool for the Synthesis and Mining of Petri Nets

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    International Conference on Application of Concurrency to System Design
    Presentation's date: 2009-07
    Presentation of work at congresses

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  • ALGORISMIA, BIOINFORMÀTICA, COMPLEXITAT I METODES FORMALS (ALBCOM)

     Orejas Valdes, Fernando; Galceran Oms, Marc; Oliva Valls, Sergi; Godoy Balil, Guillermo; Atserias Peri, Albert; Martinez Parra, Conrado; Pasarella Sanchez, Ana Edelmira; Pino Blanco, Elvira Patricia; Alvarez Faura, Maria Del Carme; Blum, Christian Clemens; Gabarro Valles, Joaquin; Cortadella Fortuny, Jordi; Molinero Albareda, Xavier; Serna Iglesias, Maria Jose; Messeguer Peypoch, Xavier; Roura Ferret, Salvador; Blesa Aguilera, Maria Jose; Valiente Feruglio, Gabriel Alejandro; Duch Brown, Amalia; Carmona Vargas, Jose; Hernandez Pibernat, Hugo; Gel Moreno, Bernat; Gascon Caro, Adrian; Petit Silvestre, Jordi; Diaz Cort, Jose Maria
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  • Divide-and-conquer strategies for process mining

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    International Conference on Business Process Management
    Presentation's date: 2009-09-09
    Presentation of work at congresses

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  • Retiming and Recycling for Elastic Systems with Early Evaluation

     Bufistov, Dmitry; Cortadella Fortuny, Jordi; Galceran Oms, Marc; Julvez Bueno, Jorge Emilio; Kishinevsky, Mike
    Design, Automation and Test in Europe
    Presentation's date: 2009-07
    Presentation of work at congresses

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  • Access to the full text
    Scheduling synchronous elastic designs  Open access  awarded activity

     Carmona Vargas, Jose; Julvez Bueno, Jorge Emilio; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    International Conference on Application of Concurrency to System Design
    Presentation's date: 2009
    Presentation of work at congresses

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    Asynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays of communication resources of a system. This flexibility comes at the expense of including a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previous approaches, this can be achieved with low complexity algorithms and without extra circuitry.

    Asynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays of communication resources of a system. This flexibility comes at the expense of including a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previous approaches, this can be achieved with low complexity algorithms and without extra circuitry.

    Best Paper Award, Ninth International Conference on Application of Concurrency to System Design.

  • Speculation in Elastic Systems

     Galceran Oms, Marc; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    Design, Automation and Test in Europe
    Presentation's date: 2009-07
    Presentation of work at congresses

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  • Elasticity and Petri Nets

     Cortadella Fortuny, Jordi; Kishinevsky, M; Bufistov, Dmitry; Carmona Vargas, Jose; Julvez Bueno, Jorge Emilio
    Lecture notes in computer science
    Date of publication: 2008-01
    Journal article

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  • Elasticity and Petri Nets

     Cortadella Fortuny, Jordi; Kishinevsky, M; Bufistov, Dmitry; Carmona Vargas, Jose; Júlvez, J
    Transactions on petri nets and other models of concurrency
    Date of publication: 2008-08
    Journal article

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  • Encoding Large Asynchronous Controllers With ILP Techniques

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2008-01
    Journal article

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  • Formal methods for the analysis and synthesis of nanometer-scale cellular arrays

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Yousuke, Takada; Ferdinand, Peper
    ACM journal on emerging technologies in computing systems
    Date of publication: 2008-04
    Journal article

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  • Performance-preserving clustering of elastic controllers

     Carmona Vargas, Jose; Julvez Bueno, Jorge Emilio; Cortadella Fortuny, Jordi
    Date: 2008-02
    Report

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  • Logic Synthesis Techniques for High-Speed Circuits

     Bañeres Besora, David
    Defense's date: 2008-02-19
    Department of Computer Science, Universitat Politècnica de Catalunya
    Theses

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  • A Symbolic Algorithm for the Synthesis of Bounded Petri nets

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex
    29th INTERNATIONAL CONFERENCE ON APPLICATION AND THEORY OF PETRI NETS AND OTHER MODELS OF CONCURRENCY
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  • A region-based algorithm for discovering Petri nets from event logs

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Kishinevsky, Michael
    6th International Conference on Business Process Management
    Presentation of work at congresses

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  • International Conference on Computer Aided Design (ICCAD)

     Cortadella Fortuny, Jordi; Galceran Oms, Marc
    International Conference on Computer Aided Design (ICCAD)
    Presentation of work at congresses

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  • Automating synthesis of asynchronous communication mechanisms

     Gorgonio, K; Cortadella Fortuny, Jordi; Xia, F; Yakovlev, A
    Fundamenta informaticae
    Date of publication: 2007-01
    Journal article

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  • The octahedron abstract domain

     Cortadella Fortuny, Jordi
    Science of computer programming
    Date of publication: 2007-01
    Journal article

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  • Compilers

     Cortadella Fortuny, Jordi
    Date: 2007-09-01
    Report

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  • Layout-aware gate duplication and buffer insertion

     Bañeres, David; Cortadella Fortuny, Jordi; Kishinevsky, Michael
    Design Automation & Test in Europe
    Presentation of work at congresses

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  • Métodos formales y algoritmos para el diseño de sistemas

     Xhafa Xhafa, Fatos; Orejas Valdes, Fernando; Godoy Balil, Guillermo; Costa Gorgônio, Kyller; Oliva Valls, Sergi; Galceran Oms, Marc; Gascon Caro, Adrian; Gel Moreno, Bernat; Hernandez Pibernat, Hugo; Duch Brown, Amalia; Blum, Christian Clemens; Pasarella Sanchez, Ana Edelmira; Diaz Cort, Jose Maria; Pino Blanco, Elvira Patricia; Petit Silvestre, Jordi; Alvarez Faura, Maria Del Carme; Blesa Aguilera, Maria Jose; Gabarro Valles, Joaquin; Cortadella Fortuny, Jordi; Serna Iglesias, Maria Jose; Carmona Vargas, Jose
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  • Synchronous elastic circuits with early evaluation and token counterflow

     Cortadella Fortuny, Jordi; Kishinevsky, M
    Design Automation Conference
    Presentation of work at congresses

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  • A Compositional Method for the Synthesis of Asynchronous Communication Mechanisms

     Cortadella Fortuny, Jordi; Gorgônio, Kyller Costa; Fei, Xia
    Date of publication: 2007-06-30
    Book chapter

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  • Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

     Cortadella Fortuny, Jordi; Kondratyev, Alex; Christos, Luciano Lavagno And Sotiriou
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2006-10
    Journal article

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  • Synthesis of asynchronous controllers using integer linear programming

     Carmona Vargas, Jose; Colom, José M; Cortadella Fortuny, Jordi
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2006-09
    Journal article

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