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    Metastability in better-than-worst-case designs  Open access

     Beer, Salomon; Cannizzaro, Marco; Cortadella Fortuny, Jordi; Ginosar, Ran; Lavagno, Luciano
    International Symposium on Asynchronous Circuits and Systems
    p. 101-102
    DOI: 10.1109/ASYNC.2014.21
    Presentation's date: 2014-05
    Presentation of work at congresses

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    Better-Than-Worst-Case-Designs use timing speculation to run with a cycle period faster than the one required for worst-case conditions. This speculation may produce timing violations and metastability that result in failures and non-deterministic timing behavior. The effects of these phenomena are not always well understood by designers and researchers in this area. This paper analyzes the impact of timing speculation and the reasons why it is difficult to adopt this paradigm in industrial designs.

    Postprint (author’s final draft)

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    Hardware primitives for the synthesis of multithreaded elastic systems  Open access

     Dimitrakopoulos, George N.; Seitanidis, I.; Psarras, A.; Tsiouris, K.; Mattheakis, Pavlos M.; Cortadella Fortuny, Jordi
    Design, Automation and Test in Europe
    p. 1-4
    DOI: 10.7873/DATE2014.314
    Presentation's date: 2014-03
    Presentation of work at congresses

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    Elastic systems operate in a dataflow-like mode using a distributed scalable control and tolerating variable-latency computations. At the same time, multithreading increases the utilization of processing units and hides the latency of each operation by time-multiplexing operations of different threads in the datapath. This paper proposes a model to unify multithreading and elasticity. A new multithreaded elastic control protocol is introduced supported by low-cost elastic buffers that minimize the storage requirements without sacrificing performance. To enable the synthesis of multithreaded elastic architectures, new hardware primitives are proposed and utilized in two circuit examples to prove the applicability of the proposed approach

    Elastic systems operate in a dataflow-like mode using a distributed scalable control and tolerating variable-latency computations. At the same time, multithreading increases the utilization of processing units and hides the latency of each operation by time-multiplexing operations of different threads in the datapath. This paper proposes a model to unify multithreading and elasticity. A new multithreaded elastic control protocol is introduced supported by low-cost elastic buffers that minimize the storage requirements without sacrificing performance. To enable the synthesis of multithreaded elastic architectures, new hardware primitives are proposed and utilized in two circuit examples to prove the applicability of the proposed approach.

    Postprint (author’s final draft)

  • Algorísmia, Bioinformàtica, Complexitat i Mètodes Formals

     Cortadella Fortuny, Jordi; Orejas Valdes, Fernando; Martinez Parra, Conrado; Serna Iglesias, Maria Jose; Alvarez Faura, Maria Del Carme; Gabarro Valles, Joaquin; Atserias Peri, Albert; Messeguer Peypoch, Xavier; Petit Silvestre, Jordi; Pino Blanco, Elvira Patricia; Roura Ferret, Salvador; Valiente Feruglio, Gabriel Alejandro; Carmona Vargas, Jose; Godoy Balil, Guillermo; Duch Brown, Amalia; Blesa Aguilera, Maria Jose; Molter, Hendrik; De San Pedro Martín, Javier; Muñoz Gama, Jorge; Diaz Cort, Jose Maria
    Competitive project

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  • Modelos y métodos computacionales para datos masivos estructurados

     Diaz Cort, Jose Maria; Cortadella Fortuny, Jordi; Serna Iglesias, Maria Jose; Alvarez Faura, Maria Del Carme; Pino Blanco, Elvira Patricia; Carmona Vargas, Jose; Gabarro Valles, Joaquin; Xhafa Xhafa, Fatos; Pasarella Sanchez, Ana Edelmira; Petit Silvestre, Jordi; Mylonakis Pascual, Nicolas Eduardo; Martinez Parra, Conrado; Duch Brown, Amalia; Godoy Balil, Guillermo; Roura Ferret, Salvador; Roca Perez, Antoni; Soares Ribeiro, Joel Tiago; Pérez Giménez, Xavier; Orejas Valdes, Fernando
    Competitive project

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  • Membre de l'Academia Europaea

     Cortadella Fortuny, Jordi
    Award or recognition

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  • Automatic Synthesis and Optimization of Chip Multiprocessors  Open access

     Nikitin, Nikita
    Universitat Politècnica de Catalunya
    Theses

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    NikitinLa tecnología de microprocesadores ha experimentado un crecimiento importante durante las últimas décadas. La rápida miniaturización de la tecnología CMOS ha causado un incremento de las frecuencias de operación y del rendimiento por unidad de área, enfrentándose al problema fundamental de disipación de energía. Los Multiprocesadores en Chip (CMPs) se han convertido en el último paradigma para mejorar la eficiencia de consumo y rendimiento de los sistemas de computación, aprovechando el paralelismo inherente en las aplicaciones. Los prototipos y las implementaciones industriales han demostrado los beneficios obtenidos por los CMPs con cientos de núcleos.Los diseñadores de CMPs se enfrentan a numerosas y complicadas decisiones. Algunas de ellas son:- ¿Cuál debería ser el ratio entre el área de los núcleos y el área de la memoria en un chip?- ¿Qué arquitectura de núcleo se debería seleccionar?- ¿Cuántos niveles de jerarquía debería tener el subsistema de memoria?- ¿Qué topologías de interconexión proporcionan una comunicación eficiente en chip?Éstos y muchos otros aspectos crean un espacio complejo multidimensional para la exploración de la arquitectura. Las herramientas para la automatización del diseño empiezan a ser esenciales para hacer factible la exploración de arquitectura, dadas las restricciones del tiempo de comercialización. Los métodos de exploración deben ser eficientes y escalables para aplicarse a las futuras arquitecturas en chip con cientos o miles de núcleos.Una vez fabricados, los CMPs necesitan estrategias para la maximizar su rendimiento. Se necesitan métodos inteligentes para la asignación y planificación de tareas para garantizar el uso total de los beneficios de los procesadores con muchos núcleos. Estos métodos deben tener en cuenta las particularidades de las arquitecturas modernas, como las técnicas avanzadas para ahorro de consumo y las jerarquías complejas de memoria.Esta tesis tiene distintos objetivos. El primero es proponer métodos para el modelado analítico eficiente y la exploración de la arquitectura de CMPs. La eficiencia se consigue mediante el uso de modelos analíticos en lugar de simulaciones, y la sustitución de la exploración exhaustiva con una estrategia de búsqueda inteligente. Además, estos métodos incorporan modelos de alto nivel para la planificación física. Las contribuciones relacionadas están descritas en los Capítulos 3, 4 y 5 del documento.El segundo objetivo de este trabajo es proponer un algoritmo escalable para la asignación de tareas para los CMPs de propósito general con técnicas de control de consumo, para la utilización eficiente de los sistemas de muchos núcleos. Esta contribución se detalla en el Capítulo 6 de la tesis.Finalmente, el tercer objetivo de esta tesis es considerar los aspectos del diseño y la exploración de las interconexiones en chip, y desarrollar un modelo para optimizar conjuntamente el encaminamiento de mensajes y la asignación de canales en las redes de inteconexión. La metodología desarrollada puede ser aplicada a varias clases de sistemas en chip, desde los procesadores de propósito general hasta los sistemas para aplicaciones específicas. El Capítulo 7 describe el modelo propuesto.Los métodos presentados han sido comprobados metódicamente mediante experimentos, cuyos resultados están descritos en esta tesis. Al final del documento se proponen unas posibles direcciones para trabajo futuro.

    The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental issue of power dissipation. Chip Multiprocessors (CMPs) have become the latest paradigm to improve the power-performance efficiency of computing systems by exploiting the parallelism inherent in applications. Industrial and prototype implementations have already demonstrated the benefits achieved by CMPs with hundreds of cores.CMP architects are challenged to take many complex design decisions. Only a few of them are:- What should be the ratio between the core and cache areas on a chip?- Which core architectures to select?- How many cache levels should the memory subsystem have?- Which interconnect topologies provide efficient on-chip communication?These and many other aspects create a complex multidimensional space for architectural exploration. Design Automation tools become essential to make the architectural exploration feasible under the hard time-to-market constraints. The exploration methods have to be efficient and scalable to handle future generation on-chip architectures with hundreds or thousands of cores.Furthermore, once a CMP has been fabricated, the need for efficient deployment of the many-core processor arises. Intelligent techniques for task mapping and scheduling onto CMPs are necessary to guarantee the full usage of the benefits brought by the many-core technology. These techniques have to consider the peculiarities of the modern architectures, such as availability of enhanced power saving techniques and presence of complex memory hierarchies.This thesis has several objectives. The first objective is to elaborate the methods for efficient analytical modeling and architectural design space exploration of CMPs. The efficiency is achieved by using analytical models instead of simulation, and replacing the exhaustive exploration with an intelligent search strategy. Additionally, these methods incorporate high-level models for physical planning. The related contributions are described in Chapters 3, 4 and 5 of the document.The second objective of this work is to propose a scalable task mapping algorithm onto general-purpose CMPs with power management techniques, for efficient deployment of many-core systems. This contribution is explained in Chapter 6 of this document.Finally, the third objective of this thesis is to address the issues of the on-chip interconnect design and exploration, by developing a model for simultaneous topology customization and deadlock-free routing in Networks-on-Chip. The developed methodology can be applied to various classes of the on-chip systems, ranging from general-purpose chip multiprocessors to application-specific solutions. Chapter 7 describes the proposed model.The presented methods have been thoroughly tested experimentally and the results are described in this dissertation. At the end of the document several possible directions for the future research are proposed.

  • Physical planning for the architectural exploration of large-scale chip multiprocessors

     De San Pedro Martín, Javier; Nikitin, Nikita; Cortadella Fortuny, Jordi; Petit Silvestre, Jordi
    IEEE/ACM International Symposium on Networks-on-Chip
    p. 1-2
    DOI: 10.1109/NoCS.2013.6558399
    Presentation's date: 2013
    Presentation of work at congresses

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    This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout constraints that enforce regularity in the interconnect networks. Routing is performed on top of memories and components that underutilize the available metal layers for interconnectivity. The experiments demonstrate the impact of physical parameters in the selection of the most efficient architectures. Thus, the integrated flow contributes to deliver physically-viable architectures and simplify the complex design closure of large-scale CMPs.

  • Physical-aware system-level design for tiled hierarchical chip multiprocessors

     Cortadella Fortuny, Jordi; De San Pedro Martín, Javier; Nikitin, Nikita; Petit Silvestre, Jordi
    ACM International Symposium on Physical Design
    p. 3-10
    DOI: 10.1145/2451916.2451920
    Presentation's date: 2013
    Presentation of work at congresses

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    Tiled hierarchical architectures for Chip Multiprocessors (CMPs) represent a rapid way of building scalable and power-efficient many-core computing systems. At the early stages of the design of a CMP, physical parameters are often ignored and postponed for later design stages. In this work, the importance of physical-aware system-level exploration is investigated, and a strategy for deriving chip floorplans is described. Additionally, wire planning of the on-chip interconnect is performed, as its topology and organization affect the physical layout of the system. Traditional algorithms for floorplanning and wire planning are customized to include physical constraints specific for tiled hierarchical architectures. Over-the-cell routing is used as one of the major area savings strategy. The combination of architectural exploration and physical planning is studied with an example and the impact of the physical aspects on the selection of architectural parameters is evaluated.

  • Static task mapping for tiled chip multiprocessors with multiple voltage islands

     Nikitin, Nikita; Cortadella Fortuny, Jordi
    International Conference on Architecture of Computing Systems
    p. 50-62
    DOI: 10.1007/978-3-642-28293-5_5
    Presentation's date: 2012-03
    Presentation of work at congresses

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    The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping onto general-purpose CMPs with multiple pre-defined voltage islands for power management. The CMPs are assumed to contain different classes of processing elements with multiple voltage/frequency execution modes to better cover a large range of applications. Task mapping is performed with awareness of both on-chip and off-chip memory traffic, and communication constraints such as the link and memory bandwidth. A novel mapping approach based on Extremal Optimization is proposed for large-scale CMPs. This new combinatorial optimization method has delivered very good results in quality and computational cost when compared to the classical simulated annealing.

  • Integrating formal verification in an online judge for e-Learning logic circuit design

     De San Pedro Martín, Javier; Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Petit Silvestre, Jordi
    ACM Technical Symposium on Computer Science Education
    p. 451-456
    DOI: 10.1145/2157136.2157268
    Presentation's date: 2012
    Presentation of work at congresses

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  • Analytical performance modeling of hierarchical interconnect fabrics

     Nikitin, Nikita; De San Pedro Martín, Javier; Carmona Vargas, Jose; Cortadella Fortuny, Jordi
    IEEE/ACM International Symposium on Networks-on-Chip
    p. 107-114
    DOI: 10.1109/NOCS.2012.20
    Presentation's date: 2012
    Presentation of work at congresses

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    Measuring the tolerance of self-adaptive clocks to supply voltage noise  Open access

     Perez Puigdemont, Jordi; Moll Echeto, Francesc de Borja; Cortadella Fortuny, Jordi
    Conference on Design of Circuits and Integrated Systems
    p. 399-404
    Presentation's date: 2011-11-18
    Presentation of work at congresses

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    Simultaneous switching noise has become an important issue due to its signal integrity and timing implications. Therefore a lot of time and resources are spent during the PDN design to minimize the supply voltage variation. This paper presents the self-adaptive clock as an alternative to tolerate the critical path delay variation due to supply noise thanks to its self-adaptable nature. A self-adaptive clock generation circuit is proposed in this paper and its benefits, in terms of clock period reduction, are assessed under a realistic supply noise obtained through simulation for different switching activities.

  • Automatic Pipelining of Elastic Systems

     Galceran Oms, Marc
    Department of Computer Science, Universitat Politècnica de Catalunya
    Theses

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  • PERFOMANCE OPTIMIZATION OF ELASTIC SYSTEMS

     DMITRY, BUFISTOV
    Department of Computer Science, Universitat Politècnica de Catalunya
    Theses

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  • TOWARDS THE AUTOMATIC SYNTHESIS OF ASYNCHRONOUS COMMUNICATION MECHANISMS

     Costa Gorgônio, Kyller
    Department of Computer Science, Universitat Politècnica de Catalunya
    Theses

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  • Introduction to programming

     Cortadella Fortuny, Jordi; Gavaldà Mestre, Ricard; Orejas Valdes, Fernando
    Date: 2010-09-01
    Report

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  • ALGORISMIA, BIOINFORMÀTICA, COMPLEXITAT I METODES FORMALS (ALBCOM)

     Orejas Valdes, Fernando; Galceran Oms, Marc; Oliva Valls, Sergi; Godoy Balil, Guillermo; Atserias Peri, Albert; Martinez Parra, Conrado; Pasarella Sanchez, Ana Edelmira; Pino Blanco, Elvira Patricia; Alvarez Faura, Maria Del Carme; Blum, Christian Clemens; Gabarro Valles, Joaquin; Cortadella Fortuny, Jordi; Molinero Albareda, Xavier; Serna Iglesias, Maria Jose; Messeguer Peypoch, Xavier; Roura Ferret, Salvador; Blesa Aguilera, Maria Jose; Valiente Feruglio, Gabriel Alejandro; Duch Brown, Amalia; Carmona Vargas, Jose; Hernandez Pibernat, Hugo; Gel Moreno, Bernat; Gascon Caro, Adrian; Petit Silvestre, Jordi; Diaz Cort, Jose Maria
    Competitive project

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  • Divide-and-conquer strategies for process mining

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    International Conference on Business Process Management
    p. 327-343
    DOI: 10.1007/978-3-642-03848-8_22
    Presentation's date: 2009-09-09
    Presentation of work at congresses

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  • Genet: a Tool for the Synthesis and Mining of Petri Nets

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    International Conference on Application of Concurrency to System Design
    p. 181-185
    Presentation's date: 2009-07
    Presentation of work at congresses

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  • Retiming and Recycling for Elastic Systems with Early Evaluation

     Bufistov, Dmitry; Cortadella Fortuny, Jordi; Galceran Oms, Marc; Julvez Bueno, Jorge Emilio; Kishinevsky, Mike
    Design, Automation and Test in Europe
    p. 288-291
    DOI: 10.1145/1629911.1629988
    Presentation's date: 2009-07
    Presentation of work at congresses

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  • Speculation in Elastic Systems

     Galceran Oms, Marc; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    Design, Automation and Test in Europe
    p. 292-295
    Presentation's date: 2009-07
    Presentation of work at congresses

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  • A recursive approach for Process Mining

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi
    Date: 2009-02
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  • Region-based Algorithms for Process Mining and Synthesis of Petri Nets

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi
    Date: 2009-02
    Report

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    Scheduling synchronous elastic designs  Open access  awarded activity

     Carmona Vargas, Jose; Julvez Bueno, Jorge Emilio; Cortadella Fortuny, Jordi; Kishinevsky, Mike
    International Conference on Application of Concurrency to System Design
    p. 52-59
    DOI: DOI 10.1109/ACSD.2009.12
    Presentation's date: 2009
    Presentation of work at congresses

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    Asynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays of communication resources of a system. This flexibility comes at the expense of including a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previous approaches, this can be achieved with low complexity algorithms and without extra circuitry.

    Best Paper Award, Ninth International Conference on Application of Concurrency to System Design.

  • Performance-preserving clustering of elastic controllers

     Carmona Vargas, Jose; Julvez Bueno, Jorge Emilio; Cortadella Fortuny, Jordi
    Date: 2008-02
    Report

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  • Logic Synthesis Techniques for High-Speed Circuits

     Bañeres Besora, David
    Department of Computer Science, Universitat Politècnica de Catalunya
    Theses

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  • A region-based algorithm for discovering Petri nets from event logs

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Kishinevsky, Michael
    6th International Conference on Business Process Management
    p. 358-373
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  • A Symbolic Algorithm for the Synthesis of Bounded Petri nets

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex
    29th INTERNATIONAL CONFERENCE ON APPLICATION AND THEORY OF PETRI NETS AND OTHER MODELS OF CONCURRENCY
    p. 92-111
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  • International Conference on Computer Aided Design (ICCAD)

     Cortadella Fortuny, Jordi; Galceran Oms, Marc
    International Conference on Computer Aided Design (ICCAD)
    p. 434-441
    Presentation of work at congresses

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  • Métodos formales y algoritmos para el diseño de sistemas

     Xhafa Xhafa, Fatos; Orejas Valdes, Fernando; Godoy Balil, Guillermo; Costa Gorgônio, Kyller; Oliva Valls, Sergi; Galceran Oms, Marc; Gascon Caro, Adrian; Gel Moreno, Bernat; Hernandez Pibernat, Hugo; Duch Brown, Amalia; Blum, Christian Clemens; Pasarella Sanchez, Ana Edelmira; Diaz Cort, Jose Maria; Pino Blanco, Elvira Patricia; Petit Silvestre, Jordi; Alvarez Faura, Maria Del Carme; Blesa Aguilera, Maria Jose; Gabarro Valles, Joaquin; Cortadella Fortuny, Jordi; Serna Iglesias, Maria Jose; Carmona Vargas, Jose
    Competitive project

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  • Compilers

     Cortadella Fortuny, Jordi
    Date: 2007-09-01
    Report

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  • A Compositional Method for the Synthesis of Asynchronous Communication Mechanisms

     Cortadella Fortuny, Jordi; Gorgônio, Kyller Costa; Fei, Xia
    Date of publication: 2007-06-30
    Book chapter

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  • Layout-aware gate duplication and buffer insertion

     Bañeres, David; Cortadella Fortuny, Jordi; Kishinevsky, Michael
    Design Automation & Test in Europe
    p. 1367-1372
    Presentation of work at congresses

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  • Synchronous elastic circuits with early evaluation and token counterflow

     Cortadella Fortuny, Jordi; Kishinevsky, M
    Design Automation Conference
    p. 416-419
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  • Synchronous elastic circuits

     Cortadella Fortuny, Jordi; Kishinevsky, M; Grundmann, Bill; O'Leary, S Krstic and J
    Date of publication: 2006-06-30
    Book chapter

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  • State encoding of large asynchronous controllers

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi
    ACM/IEEE Design Automation Conference
    p. 939-944
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  • Dominator based partitioning for delay optimization

     Bañeres Besora, David; Cortadella Fortuny, Jordi; Kishinevsky, M
    16th ACM Great Lakes Symposium on VLSI
    p. 67-72
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  • SELF: Specification and design of synchronous elastic circuits

     Cortadella Fortuny, Jordi; Kishinevsky, M; Grundmann, Bill
    ACM/IEEE International Workshop on Timing Issues
    p. 16-21
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  • Performance analysis of concurrent systems with early evaluation

     Julvez Bueno, Jorge Emilio; Cortadella Fortuny, Jordi; Kishinevsky, Michael
    2006 International Conference on Computer-Aided Design
    p. 448-455
    Presentation of work at congresses

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  • Synthesis of synchronous elastic architectures

     Cortadella Fortuny, Jordi; Kishinevsky, M; Grundmann, Bill
    ACM/IEEE Design Automation Conference
    p. 657-662
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  • From molecular interactions to gates: a systematic approach

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Yousuke, Takada; Ferdinand, Peper
    2006 International Conference on Computer-Aided Design
    p. 891-898
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  • Dominator-based partitioning for delay optimization

     Bañeres Besora, David; Cortadella Fortuny, Jordi; Kishinevsky, M
    16th ACM Great Lakes Symposium on VLSI
    p. 67-72
    Presentation of work at congresses

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  • Synchronous Elastic Networks

     Krstic, Sava; Cortadella Fortuny, Jordi; Kishinevsky, Michael; O'Leary, John
    International Conference on Formal Methods in Computer-Aided Design
    p. 19-30
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  • ABSTRACT INTERPRETATION TECHNIQUES FOR THE VERIFICATION OF TIMED SYSTEMS

     Clariso Viladrosa, Robert
    Department of Computer Science, Universitat Politècnica de Catalunya
    Theses

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  • Verification of Concurrent Systems with Parametric Delays Using Octahedra

     CLARISO, R; Cortadella Fortuny, Jordi
    5th International Conference on Application of Concurrency to System Design
    p. 118-121
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  • Automating the Synthesis of Asynchronous Communication Mechanisms

     Cortadella Fortuny, Jordi; Gorgonio, K; Xia, F; Yakovlev, A
    5th International Conference on Application of Concurrency to System Design
    p. 166-175
    Presentation of work at congresses

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  • Resource-Constrained Software Pipelining for High-level Synthesis of DSP Systems

     Sanchez Carracedo, Fermin; Cortadella Fortuny, Jordi
    3rd International workshopon Algorithms and Parallel VLSI arcuitectures
    p. 377-388
    Presentation's date: 2004-08
    Presentation of work at congresses

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  • Synthesis of Asynchronous Hardware from Petri Nets

     Carmona Vargas, Jose; Cortadella Fortuny, Jordi; Khomenko, V; Yakovlev, A
    Date of publication: 2004-04-30
    Book chapter

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