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    Systematic and random variability analysis of two different 6T-SRAM layout topologies  Open access

     Amat Bertran, Esteve; Amatlle, E.; Gomez Gonzalez, Sergio; Aymerich Capdevila, Nivard; Garcia Almudever, Carmen; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Microelectronics journal
    Date of publication: 2013-09
    Journal article

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    This paper studies the device variability influence on 6T-SRAM cells in a function of the regularity level of their layout. Systematic and random variations have been analyzed when these memory circuits are implemented on a 45 nm technology node. The NBTI aging relevance on these cells has been also studied for two layout topologies and SNM has been seen as the parameter that suffers the highest impact with respect to cell aging and variability.

  • Adaptive fault-tolerant architecture for unreliable device technologies

     Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio
    Date of publication: 2013-06-17
    Book chapter

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    Presentation of new advances in the area of architecture of reliable non-homogeneous fault tolerant systems.

  • Effectiveness of hybrid recovery techniques on parametric failures

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    International Symposium on Quality Electronic Design
    Presentation's date: 2013-03
    Presentation of work at congresses

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    Modern day microprocessors effectively utilise supply voltage scaling for tremendous power reduction. The minimum voltage beyond which a processor cannot operate reliably is defined as V ddmin. On-chip memories like caches are the most susceptible to voltage-noise induced failures because of process variations and reduced noise-margins thereby arbitrating whole processor's V ddmin. In this paper, we evaluate the effectiveness of a new class of hybrid techniques in improving cache yield through failure prevention and correction. Proactive read/write assist techniques like body-biasing (BB) and wordline boosting (WLB) when combined with reactive techniques like ECC and redundancy are shown to offer better quality-energy-area trade offs when compared to their standalone configurations. Proactive techniques can help lower V ddmin (improving functional margin) for significant power savings and reactive techniques ensure that the resulting large number of failures are corrected (improving functional yield). Our results in 22nm technology indicate that at scaled supply voltages, hybrid techniques can improve parametric yield by atleast 28% when considering worst-case process variations

  • Novel redundant logic design for noisy low voltage scenarios

     Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; García Leyva, Lancelot
    Latin American Symposium on Circuits and Systems
    Presentation's date: 2013-02
    Presentation of work at congresses

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    The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be predominant and the reliability of the future circuits will be limited. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic and functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value. Therefore, it avoids the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs with a practical full tolerance to input with a signal to noise ratio of 5dB. Turtle Logic in accordance to Kullback Leibler Distance noise immunity measurement for a NOT gate is approximately 3.6X, 13.4X and 20.9X times better than MRF, DCVS and standard CMOS techniques, respectively, when the gates are operate, with a power supply of 0.15 volts, a temperature of 100 oC and noisy inputs with Additive White Gaussian Noise with zero mean and a standard deviation of 60mV

    The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be predominant and the reliability of the future circuits will be limited. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic and functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value. Therefore, it avoids the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs with a practical full tolerance to input with a signal to noise ratio of 5dB. Turtle Logic in accordance to Kullback Leibler Distance noise immunity measurement for a NOT gate is approximately 3.6X, 13.4X and 20.9X times better than MRF, DCVS and standard CMOS techniques, respectively, when the gates are operate, with a power supply of 0.15 volts, a temperature of 100 oC and noisy inputs with Additive White Gaussian Noise with zero mean and a standard deviation of 60mV.

  • Reliability study on technology trends beyond 20nm

     Amat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    International Conference Mixed Design of Integrated Circuits and Systems
    Presentation's date: 2013-06-20
    Presentation of work at congresses

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    In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits based on FinFET devices have presented the best overall behavior, since we have obtained the best performance and variability robustness. Meanwhile, the III-V/Ge-based circuits have shown the best electrical masking in front of soft errors disturbances.

  • Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio; Canal Corretger, Ramon
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2013-08-05
    Presentation of work at congresses

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    3T1D-DRAM cells will still be operative with 7nm FinFETs but their performance is significantly degraded when factoring in variability. In order to improve the cell robustness against device process variation and high environment temperatures, we propose a Dual-VT strategy. Our results show a larger retention time, significant cell spread reduction and reliable behavior up to 100°C.

  • Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches

     Pouyan, Peyman; Amat Bertran, Esteve; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Design, Automation and Test in Europe
    Presentation's date: 2013-03
    Presentation of work at congresses

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    Scaling of device dimensions toward nano-scale regime has made it essential to innovate novel design techniques for improving the circuit robustness. This work proposes an implementation of adaptive proactive reconfiguration methodology that can first monitor process variability and BTI aging among 6T SRAM memory cells and then apply a recovery mechanism to extend the SRAM lifetime. Our proposed technique can extend the memory lifetime between 2X to 4.5X times with a silicon area overhead of around 10% for the monitoring units, in a 1kB 6T SRAM memory chip.

  • Extending the fundamental error bounds for asymmetric error reliable computation

     Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio
    IEEE/ACM International Symposium on Nanoscale Architectures
    Presentation's date: 2013-07-17
    Presentation of work at congresses

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    Future computing systems based on new emerging nanotechnologies will have to rely on very high failure rate devices. Therefore, the study of fault-tolerant architectures is of great interest today. One of the most challenging problems of this research area consists in finding the fundamental error bounds beyond which reliable computation is not possible. In the literature we can find the exact error threshold for circuits built out of noisy NAND gates under the von Neumann's probabilistic computing framework. In this paper we extend this result for asymmetric error designs and demonstrate that it is possible to compute reliably with 2-input noisy NAND gates beyond the well known error bound: ¿* = (3 - v7)/4.

  • A single event transient hardening circuit design technique based on strengthening

     Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2013-08-06
    Presentation of work at congresses

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  • Impact of finfet and III-V/Ge technology on logic and memory cell behavior

     Amat, Esteve; Calomarde Palomino, Antonio; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    IEEE transactions on device and materials reliability
    Date of publication: 2013-11-20
    Journal article

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    In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios (variability and soft errors). FinFET-based circuits show the highest robustness against variability and soft error environments.

  • Controlled degradation stochastic resonance in adaptive averaging cell-based architectures

     Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio
    IEEE transactions on nanotechnology
    Date of publication: 2013-11
    Journal article

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    In this paper, we first analyze the degradation stochastic resonance (DSR) effect in the context of adaptive averaging (AD-AVG) architectures. The AD-AVG is the adaptive version of the well-known AVG architecture. It is an optimized fault-tolerant design for future technologies with very high rates of failures and defects. With system degradation the AD-AVG reliability is diminishing, as expected, but at a certain moment in time it increases due to the DSR occurrence, which is counterintuitive. We study this phenomenon under various redundancy levels and noise condition. If we take for example a 20-input AD-AVG with particular noise conditions, our simulations indicate an initial yield decrease from 1 to 0.89 with the system degradation, then a grow up to 0.94 at the DSR peak, and finally a decrease to zero when the system is reaching its end of life. Subsequently, we introduce a method to induce DSR in an AD-AVG structure, regardless of the degradation level, when this results in reliability improvement. To achieve this, we augment the AD-AVG with per input controllable noise injectors that can be utilized to induce virtual circuit degradation and create the required conditions for the DSR peak appearance. With this scheme the beneficial DSR effect is created even though the actual DSR system degradation (aging conditions) is not reached. This allows us to provide an optimum and nearly flat reliability level at any time before the DSR peak degradation level. Our experiments suggest that when we apply this method to the same 20-input AD-AVG, we obtain a guaranteed yield level of 0.94 from fresh devices to the DSR peak degradation level with a maximum yield of 0.97. In this way, a minimum yield level can be guaranteed, by determining at design time the required AD-AVG redundancy that provides it, for the entire life of the system. © 2002-2012 IEEE.

  • Impact of FinFET technology introduction in the 3T1D-DRAM memory cell

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    IEEE transactions on device and materials reliability
    Date of publication: 2013-01-09
    Journal article

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    n this paper, the 3T1D-DRAM cell based on FinFET devices is studied as an alternative to the bulk one. We observe an improvement in its behavior when IG and SG FinFETs are properly mixed, since together they provide a relevant increase in the memory circuit retention time. Moreover, our FinFET cell shows larger variability robustness, better performance at low supply voltage, and higher tolerance to elevated temperatures.

  • Variability-aware Architectures based on Hardware Redundancy for Nanoscale Reliable Computation

     Aymerich Capdevila, Nivard
    Defense's date: 2013-12-16
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    Durant les últimes dècades, la humanitat ha experimentat una gran millora en la qüalitat de vida gràcies a la ràpida evolució dels circuits integrats (IC). Aquesta carrera sense precedents, acompanyada d¿un gran impacte econòmic, s¿ha basat en la producció de sistemes de processat complexes a partir de components molt fiables. No obstant, la hipòtesi fonamental de components quasi-ideals, que ha estat certa en les generacions CMOS passades, sembla que avui arriba a la seva fi. De fet, a mesura que la tecnologia MOSFET es miniaturitza a nivells de nanoescala s¿apropa a limits físics fonamentals i comença a experimentar nivells més alts de variabilitat, degradació de característiques i taxes de defectes de producció. Per altra banda, circuits integrats amb un nombre de transistors cada vegada més gran requereixen una reducció en la taxa de fallades per dispositiu per tal de mantenir un nivell de fiabilitat global constant. Com a resultat, cada vegada és més important el desenvolupament d¿arquitectures de circuit capaçes de proporcioniar computació fiable i tolerar alhora nivells de variabilitat i defectes més grans.L¿objectiu principal d¿aquesta tesi és proposar i analitzar noves arquitectures tolerants a fallades basades en la redundància per a les tecnologies futures. La nostra investigació es fonamenta en els principis de la redundància establerts per von Neumann en els anys 1950 i els extén en tres noves dimensions:1. Heterogeneitat: La majoria de treballs sobre arquitectures tolerants a fallades basades en la redundància assumeixen un nivell de variabilitat homogeni en les rèpliques tal com es fa en el treball original de von Neumann. En canvi, nosaltres explorem les possibilitats de la redundància quan es té en compte la heterogeneïtat entre les rèpliques. En aquest sentit, proposem mecanismes de compensació que sel¿leccionen els pesos adequats per a maximitzar la fiabilitat global.2. Asincronia: Cadascuna de les rèpliques d¿un sistema redundant pot tenir associat un temps de processat diferent degut a la variabilitat i la degradació; especialment en les futures tecnologies. Si dissenyem el nostre sistema per a treballar de manera asíncrona localment aleshores podem considerar diferents polítiques de votació. En funció de quantes rèpliques rebem abans de prendre una decisió aleshores podem obtenir diferents balanços entre el temps de processat i la fiabilitat. Nosaltres proposem un mecanisme per proporcionar aquestes facilitats i analitzem el seu funcionament.3. Jerarquia: Finalment explorem les possibilitats de la redundància aplicada a diverses capes de jerarquia en sistemes de processat complexes. Nosaltres proposem distribuir la redundància a diversos nivells de jerarquia i analitzem els beneficis obtinguts.Especulant en l¿escenari de les futures tecnologies de circuits integrats, estenem el concepte de redundància a la màxima expressió a través de l¿estudi d¿arquitectures de nano-dispositius reals. La majoria d¿arquitectures redundants fins ara no enfronten el problema de la computació a tera-escala i les tendències de la nano-tecnologia. Des de que von Neumann va aplicar per primer cop la redundància en circuits electrònics, ningú fins ara havia tractat temes tan comuns en la nanoelectrònica com la degradació i les imperfeccions en les interconneccions des del punt de vista de la redundància. En aquesta tesi adrecem de manera àmplia la fiabilitat de sistemes de processat digitals en les properes generacions tecnològiques.

  • Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio; Canal Corretger, Ramon
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2013-08
    Presentation of work at congresses

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    3T1D-DRAM cells will still be operative with 7nm FinFETs but their performance is significantly degraded when factoring in variability. In order to improve the cell robustness against device process variation and high environment temperatures, we propose a Dual-VT strategy. Our results show a larger retention time, significant cell spread reduction and reliable behavior up to 100°C.

  • Study on the optimal distribution of redundancy effort in cross-layer reliable architectures

     Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio
    IEEE International Conference on Nanotechnology
    Presentation's date: 2013-08-05
    Presentation of work at congresses

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    This paper presents a comprehensive approach to the smart application of redundancy techniques in multiple-layer hierarchical systems. Computing systems today are rapidly evolving into increasingly complex structures with an ever-increasing number of components. Moreover, future technology generations are expected to have associated lower levels of quality. For these reasons, it is emerging nowadays a renewed interest in the development of reliable architectures. In this work we delve into this topic putting special emphasis on the system hardware hierarchy. We analyze the advantages in terms of reliability of distributing redundancy effort in cross-layer systems. We base our analysis on a general fault model that takes into account both devices and interconnections. Using the Rent's Law we relate the number of devices and interconnections for different configurations of redundancy and compare the global error probability. Our results provide meaningful information about the benefits that can be achieved by properly choosing the system layer at which to apply redundancy, and if applicable, the optimal distribution of redundancy effort through the system layers. © 2013 IEEE.

  • Impact of carbon nanotube growth process imperfections on CNFET performance

     Garcia Almudever, Carmen; Rubio Sola, Jose Antonio
    Date of publication: 2012-10-24
    Book chapter

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    In silicon bulk complementary metal oxide semiconductor (CMOS) technology, the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. In the search for new technologies, carbon nanotubes are potential candidates. In this entry, we evaluate the parameter variability in carbon nanotube field effect transistors in order to analyze their real capability to be a promising alternative to Si-CMOS technology.

  • Variability analysis of carbon nanotube field effect transistors

     Garcia Almudever, Carmen; Martin-Fernandez, Iñigo; Sansa, Marc; Lora-Tamayo, E; Godignon, Philippe; Rubio Sola, Jose Antonio; Perez-Murano, Francesc
    International Conference on Micro and Nano Engineering
    Presentation's date: 2012-09-10
    Presentation of work at congresses

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  • Analysis of FinFET technology on memories

     Amat, E.; ASenov, Asen; Canal Corretger, Ramon; Cheng, B.; Cruz Diaz, Josep-llorenç; Jaksic, Zoran; Miranda, Miguel; Rubio Sola, Jose Antonio; Zuber, Paul
    IEEE International On-Line Testing Symposium
    Presentation's date: 2012-06-29
    Presentation of work at congresses

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  • Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime

     Rubio Sola, Jose Antonio; Amat Bertran, Esteve; Pouyan, Peyman
    IEEE VLSI Test Symposium
    Presentation's date: 2012-06
    Presentation of work at congresses

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    Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded SRAM memories. This work introduces a novel version that modifies and enhances the advantages of this method by considering the process variability impact on the memory components. Our results show between 30% and 45% SRAM lifetime increases over the existing proactive reconfiguration technique and between 1.7X and ~10X improvement over the non-proactive reconfiguration.

  • Shape-shifting digital hardware concept: towards a new adaptive computing system

     Rubio Sola, Jose Antonio; Garcia Almudever, Carmen; Martin, Javier; Crespo, A.; Rodriguez, Rosa; Nafria, Montse
    NASA/ESA Conference on Adaptive Hardware and Systems
    Presentation's date: 2012-07
    Presentation of work at congresses

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    In this paper a new approach to implement adaptive hardware (AH) based on memFETs crossbar structure is presented. We report a novel computing hardware principle called Shape-Shifting Digital Hardware (SSDH) oriented to execute task requirements in a dynamic, flexible, efficient and adaptive way. In this technique not only the logic functions are modifiable (as in the case of Field Programmable Gate Array, FPGA) but also the physical position of the logic elements that form the circuit. Furthermore, a new technologic strategy that allows implementing large crossbars of memFETs is introduced. The memFET is an electrically reconfigurable field effect and resistive switching device that can be used to perform logic functions and memory blocks. Into an appropriate structure such as a crossbar array, memFET allows the dynamic logic reconfiguration of the crossbar and simplify both the design and the implementation of computing hardware.

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    Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm  Open access  awarded activity

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2012
    Presentation of work at congresses

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    3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that the variability of the write access transistor has turn into the more detrimental device for the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some strategies to mitigate the cell variability.

    3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that the variability of the write access transistor has turn into the more detrimental device for the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some strategies to mitigate the cell variability.

  • Variability and reliability analysis of CNFET in the presence of carbon nanotube density fluctuation

     Garcia Almudever, Carmen; Rubio Sola, Jose Antonio
    International Conference Mixed Design of Integrated Circuits and Systems
    Presentation's date: 2012-05
    Presentation of work at congresses

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    Current carbon nanotube (CNT) synthesis processes are not perfect. One of the most critical issue is the presence of density variations in CNT growth. These variations are due to the lack of precise control of CNT location during the synthesis and the presence of metallic CNTs (m-CNTs). In this work we analyze the impact of CNT density fluctuations on carbon nanotube field effect transistor (CNFET) performance. A CNFET reliability analysis is also presented because of CNT density variations can cause a complete failure of CNFET.

  • Strain relevance on the improvement of the 3T1D cell performance

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    International Conference Mixed Design of Integrated Circuits and Systems
    Presentation's date: 2012-05-26
    Presentation of work at congresses

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  • A Novel variation-tolerant 4T-DRAM with enhance soft-error tolerance

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    IEEE International Conference on Computer Design: VLSI in Computers and Processors
    Presentation's date: 2012-09-30
    Presentation of work at congresses

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    In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment.

  • A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Eric; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    IEEE International Conference on Computer Design: VLSI in Computers and Processors
    Presentation's date: 2012-10-02
    Presentation of work at congresses

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    In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment.

    In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition to being logic-compatible, are variation tolerant and immune to noise present at low supply voltages. However, two major causes of concern are the data retention capability which is worsened by parameter variations leading to frequent data refreshes (resulting in large dynamic power overhead) and the transient reduction of stored charge increasing soft-error (SE) susceptibility. In this paper, we present a novel variation-tolerant 4T-DRAM cell whose power consumption is 20.4% lower when compared to a similar sized eDRAM cell. The retention time on-average is improved by 2.04X while incurring a delay overhead of 3% on the read-access time. Most importantly, using a soft-error (SE) rate analysis tool, we have confirmed that the cell sensitivity to SEs is reduced by 56% on-average in a natural working environment

  • Impact of bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    International Conference on Solid-State and Integrated Circuit Technology
    Presentation's date: 2012-10
    Presentation of work at congresses

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    While the feasibility of SOI or bulk substrates for 10nm FinFETs has been shown, their impact on 3T1D memory performance has not been studied yet. In our study, bulk-based FinFETs show a better behavior for golden devices. Nevertheless, when variation is factored in, SOI-based FinFETs present better tolerance and, consequently, lower performance spread than bulk-based devices. When considering environment temperature it is always a detrimental factor for both multi-gate devices, but the impact is lower for the bulk ones.

  • Degradation stochastic resonance (DSR) in AD-AVG architectures

     Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio; Cotofana, Sorin
    IEEE International Conference on Nanotechnology
    Presentation's date: 2012-08-22
    Presentation of work at congresses

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  • Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells

     Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria
    Integration. The VLSI journal
    Date of publication: 2012-06
    Journal article

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  • Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability

     Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio
    IEEE transactions on nanotechnology
    Date of publication: 2012-07
    Journal article

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    This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure that is able to cope with nonhomogeneous variability and time-varying effects like degradation and external aggressions, which are expected to be key limiting factors in future technologies. First, we consider static heterogeneity of the input variability levels and derive a methodology to determine the weight values that maximize the reliability of the averaging system. The implementation of these optimal weights in the AVG gives place to the unbalanced AVG structure (U-AVG). Second, we take into consideration that circuits are exposed to time-dependent aggression factors, which can induce significant changes on the levels of variability, and introduce the adaptive AVG structure (AD-AVG). It embeds a learning mechanism based on a variability monitor that allows for the on-line input weight adaptation such that the actual weight configuration properly reflects the aging status. To evaluate the potential implications of our proposal, we compare the conventional AVG architecture with the unbalanced (U-AVG) and the adaptive (AD-AVG) approaches in terms of reliability and redundancy overhead by means of Monte Carlo simulations. Our results indicate that when AVG and U-AVG are exposed to the same static heterogeneous variability, U-AVG requires 4$times$ less redundancy for the same reliability target. Subsequently, we include temporal variation of input drifts in the simulations to reproduce the effects of aging and external aggressions and compare the AVG structures. Our experiments suggest that AD-AVG always provides the maximum reliability and the highest tolerance against degradation. We also analyze the impact of nonideal variability monitor on the effectiveness of the AD-AVG b- havior. Finally, specific reconfigurable hardware based on resistive switching crossbar structures is proposed for the implementation of AD-AVG.

  • Variability mitigation mechanisms in scaled 3T1D-DRAM memories to 22 nm and beyond

     Amat Bertran, Esteve; Garcia Almudever, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio
    IEEE transactions on device and materials reliability
    Date of publication: 2012-09-06
    Journal article

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  • Process variability in sub-16nm bulk CMOS technology

     Rubio Sola, Jose Antonio; Figueras Pamies, Juan; Vatajelu, Elena Ioana; Canal Corretger, Ramon
    Date: 2012-03-01
    Report

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  • SRAM lifetime improvement by using adaptive proactive reconfiguration

     Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio
    International Conference Mixed Design of Integrated Circuits and Systems
    Presentation's date: 2012-05
    Presentation of work at congresses

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    Modern generations of CMOS technology nodes are facing critical causes of hardware reliability failures, which were not significant in the past. Such vulnerabilities make it essential to investigate new robust design strategies at the Nanoscale circuit system level. In this paper we have introduced an adaptive proactive reconfiguration technique that considers the inherent process variability (variability-aware) and BTI aging, and effectively enlarges the SRAM lifetime.

  • Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy

     Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio
    Microprocessors and microsystems
    Date of publication: 2012-07
    Journal article

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    One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS and new emerging research devices. The worldwide-accepted predictions with these technologies indicate a remarkable reduction of the components quality, because of the manufacturing process complexity and the erratic behavior of devices, causing a drop in the system reliability if we maintain the same design rules than today. Together with the introduction of new devices, new architectural design paradigms have to be included. Fault tolerant techniques are considered necessary and relevant in this scenario. In this paper we present a fault-tolerant nanoscale architecture based on the implementation of logic systems with Averaging Cells Linear Threshold Gates (AC-LTGs). We compare the tolerance to manufacturing and environment deviation of our approach and the well known NAND multiplexing technique. We show that the AC-LTG is a valuable alternative in specific nanoscale conditions.

  • Adaptive fault-tolerant architecture for unreliable device technologies

     Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio
    IEEE International Conference on Nanotechnology
    Presentation's date: 2011-08-19
    Presentation of work at congresses

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    This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We define an adaptive averaging cell structure (AD-AVG) that is able to cope with non-homogeneous variability and time-varying effects like degradation and external aggressions, which are expected to be a key limiting factor in future technologies. In order to achieve this goal the AD-AVG relies on the modification of the input weights so that reliable inputs have greater influence on the result than the less reliable ones. In this paper we find analytically the weight distribution that minimizes the error probability at the cell output in terms of the input variability levels. Monte Carlo based simulation results indicate that our proposal outperforms the traditional AVG at the expense of less area overhead. For the same reliability target the AD-AVG scheme requires about 70% less redundancy, when compared with the traditional balanced AVG approach.

  • Manufacturing variability analysis in carbon nanotube technology: a comparison with bulk CMOS in 6T SRAM scenario

     Garcia Almudever, Carmen; Rubio Sola, Jose Antonio
    IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
    Presentation's date: 2011-04-14
    Presentation of work at congresses

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    In silicon bulk CMOS technology the variability of the device parameters is a key drawback that may be a limiting factor for further miniaturizing nodes. New nanoscale beyond-CMOS devices are being studied such as carbon nanotubes (CNTs). The goal of this paper is to evaluate the parameter variability in Carbon Nanotube Field Effect Transistors (CNFETs) and its potential capability to be a promising alternative to Si-CMOS technology. The impact of the carbon nanotube diameter variations as well as the presence of metallic carbon nanotubes in the transistor are analyzed (device level). This variability model is used to make a comparison between Si-MOSFET and CNFET Static Random Access Memory (SRAM) 6T cells (circuit level).

  • Analysis of delay mismatching of digital circuits caused by common environmental fluctuations

     Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Cotofana, Sorin
    IEEE International Symposium on Circuits and Systems
    Presentation's date: 2011-05-16
    Presentation of work at congresses

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    Environmental conditions are changing all the time along the chip as a consequence of its own activity, provoking deviations on propagation time in digital circuits. In future technologies, the increment of devices sensitivity to environmental fluctuations yields to a wider range of possible time deviations, being for example, in an NOT gate designed in a 16nm technology 1.6 times larger than for a 45nm version. But this ratio is different for every circuit cause it depends on its fundamental structure and characteristics. In this paper the tendency of timing parameters deviations due to environmental factors fluctuation and how these deviations have deeper impact on more complex structures are analyzed. It is shown that the internal structure of the logic gates cause a mismatch between logic circuits and in future technologies it will be enlarged.

  • Carbon nanotube growth process-related variablity in CNFET's

     Garcia Almudever, Carmen; Rubio Sola, Jose Antonio
    IEEE International Conference on Nanotechnology
    Presentation's date: 2011-08-17
    Presentation of work at congresses

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  • Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    IEEE International Conference on Computer Design: VLSI in Computers and Processors
    Presentation's date: 2011
    Presentation of work at congresses

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  • A new probabilistic design methodology of nanoscale digital circuits

     García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    International Conference on Electrical Communications and Computers
    Presentation's date: 2011-02-28
    Presentation of work at congresses

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    The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is aggravated by variations caused by the difficulties of controlling Critical Dimension (CD) in nanometer technologies. The effect of variability is the difficulty in predicting and designing circuits with precise device and circuit characteristics. In this paper, a new logic design probabilistic methodology oriented to emerging and beyond CMOS in new technologies is presented, to improve tolerance to errors due to noise, defects or manufacturability errors in single gates, logic blocks or functional units. The methodology is based on the coherence of the input redundant ports using Port Redundancy (PR) and complementary redundant ports. Simulations show an excellent performance of our approach in the presence of large random noise at the inputs.

  • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

     Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Gonzalez Jimenez, Jose Luis; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Gonzalez Colas, Antonio Maria
    IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era
    Presentation's date: 2011-04-06
    Presentation of work at congresses

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    Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90 nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.

  • Design of complex circuits using the via-configurable transistor array regular layout fabric

     Pons Solé, Marc; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Gonzalez Colas, Antonio Maria
    IEEE International System-on-a-Chip Conference
    Presentation's date: 2011-09-26
    Presentation of work at congresses

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    Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new method for regular layout generation with Via-Configurable Transistor Arrays focusing on reducing the area overhead associated to regularity. Results for ISCAS85 benchmarks in the 45nm technology node are provided showing that comparable areas to the standard cell approach can be obtained.

  • TRAMS Project: variability and reliability of SRAM memories in sub-22 nm Bulk-CMOS technologies

     Canal Corretger, Ramon; Rubio Sola, Jose Antonio; ASenov, Asen; Brown, A.; Miranda, Miguel; Zuber, Paul; Gonzalez Colas, Antonio Maria; Vera, Xavier
    European Future Technologies Conference and Exhibition
    Presentation's date: 2011
    Presentation of work at congresses

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  • A comparative variability analysis for CMOS and CNFET 6T SRAM cells

     Garcia Almudever, Carmen; Rubio Sola, Jose Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2011-08
    Presentation of work at congresses

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    Statistical device variability may be a limiting factor for further miniaturizing nodes in silicon bulk CMOS technology. On the other hand, in novel technologies such as Carbon Nanotubes Field Effect Transistors (CNFETs), the device variability is also present and is mainly due to imperfections inherent in current carbon nanotube (CNT) growth methods. The goal of this paper is to evaluate the impact of the main sources of variability in conventional MOSFET and CNFET 6T SRAM cells through the consideration of random threshold voltage process variations.

  • Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells

     Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria
    ACM Great Lakes Symposium on VLSI
    Presentation's date: 2011-05-18
    Presentation of work at congresses

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    Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure could exhibit serious limitations in future CMOS technologies due to the instability caused by transistor mismatching as well as for leakage consumption reasons. For L1 data caches the new cell 3T1D DRAM is considered a potential candidate to substitute 6T SRAMs. We first evaluate the impact of the positive bias temperature instability, PBTI, on the access and retention time of the 3T1D memory cell implemented with 45 nm technology. Then, we consider all sources of variations and the effect of the degradation caused by the aging of the device on the yield at system level.

  • New reliability mechanisms in memory design for sub-22nm technologies

     Aymerich Capdevila, Nivard; Brown, A.; Canal Corretger, Ramon; Cheng, B.; Figueras Pamies, Juan; Gonzalez Colas, Antonio Maria; Herrero Abellanas, Enric; Markov, S.; Miranda, Miguel; Pouyan, Peyman; Ramirez Garcia, Tanausu; Rubio Sola, Jose Antonio; Vatajelu, I.; Vera, Xavier; Wang, W.; Zuber, Paul; ASenov, Asen
    IEEE International On-Line Testing Symposium
    Presentation of work at congresses

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  • Access to the full text
    Design guidelines towards compact litho-friendly regular cells  Open access

     Gomez Fernandez, Sergio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Elhoj, Martin; Schlinker, Guilherme; Woolaway, Nigel
    Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms
    Presentation's date: 2011-02-23
    Presentation of work at congresses

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  • New redundant logic design concept for high noise and low voltage scenarios

     García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gomez Fernandez, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Microelectronics journal
    Date of publication: 2011-12
    Journal article

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    This paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, where the thermal noise could be predominant and the reliability of the future circuits could be limited. The TL is a technology independent method, which aims to improve error tolerance when these errors are caused by noise within logic and functional units, sequential elements, and in general synchronous pipeline Finite State Machines. Turtle Logic operation is based on the consistency relation of redundant inputs. In the case of discrepancy, the out put of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. A two’s complement 8x8-bit pipelined Baugh–Wooley multiplier is implemented, on which several experiments reveal a perfect tolerance (0%errors) to single line discrepancies for both primary and internal nodes, with a cost of lost clock periods between 6% and 25%. The error ratio for the proposed Turtle Logic implementation with double discrepancies in both true and complementary lines are lower than 0.1% when the noise affects primary input nodes, and lower than 0.9% when the noise affects internal nodes.

  • ROBUSTNESS ANALYSIS OF NANOMETRIC SRAM MEMORIES

     Vatajelu, Elena Ioana
    Defense's date: 2011-09-30
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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  • Estimación del consumo de potencia a alto nivel de descripción. Nuevas técnicas

     Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
    Date of publication: 2011
    Book

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  • On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches

     Ganapathy, Shrikanth; Canal Corretger, Ramon; Gonzalez Colas, Antonio Maria; Rubio Sola, Jose Antonio
    Date: 2011-12-05
    Report

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    In this paper, we provide an insight on the different proactive read/write assist methods (wordline boosting & adaptive body biasing) that help in preventing (and reducing) parametric failures when coupled with reactive techniques like ECC and redundancy which cope with already existent failures. While proactive and reactive have been previously viewed as complementary techniques, we show that it is not necessarily the case when considering the benefits of such hybrid schemes.

    Postprint (author’s final draft)