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  • Improving multithreading performance for clustered VLIW architectures.  Open access

     Gupta, Manoj
    Defense's date: 2013-06-14
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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    Los procesadores VLIW (Very Long Instruction Word) son bastante populares como procesadores empotrados. Su uso abarca desde procesadores de señal hasta unidades gráficas. La ventaja de los procesadores VLIW es su baja complejidad y su bajo consumo energético, lo que permite unas elevadas prestaciones a un bajo coste. Su escalabilidad está limitada por el banco de registros, no es viable un procesador VLIW con un único banco de registros general debido a las limitaciones en área y consumo.Los procesadores VLIW organizados en clústeres solventan la escalabilidad del banco de registros particionando este en múltiples bancos y dividiendo las unidades funcionales en conjuntos conectados a un único banco. Con esta aproximación se puede conseguir lanzar un gran número de operaciones por ciclo manteniendo el coste de los registros relativamente bajo. Varios procesadores comerciales han sido diseñados utilizando el modelo de VLIW particionado en clústeres.Los procesadores VLIW se pueden usar para correr un amplio abanico de aplicaciones. Muchas de estas aplicaciones tienen un elevado grado de ILP (Instruction Level Parallelism), sin embargo, otras aplicaciones tienen un bajo nivel de ILP, lo que lleva a una baja utilización de los recursos del procesador. Los fallos de cache son otro motivo importante por el que los recursos del procesador son infrautilizados. La ejecución multihilo (Multithreading) permite mejorar el aprovechamiento de los recursos. Interleaved Multithreading (IMT) esconde la latencia de los fallos de cache cambiando a un hilo de ejecución distinto en cada ciclo, aunque no puede mejorar la utilización de recursos debido a un bajo ILP. SMT (Simultaneous Multithreading) puede, además, mejorar la utilización de los recursos debida a bajo ILP gracias a que combina instrucciones de distintos hilos. Desafortunadamente SMT tiene un coste considerablemente mayor que IMT.Esta tesis presenta CSMT (Cluster-level Simulataneous MultiThreading). CSMT soporta una forma limitada de SMT donde las instrucciones VLIW de distintos hilos se combinan con granularidad a nivel de clúster. Esto reduce el coste de implementación a un nivel cercano a IMT. La tesis también propone otras técnicas que permiten mejorar el rendimiento de CSMT. En particular, el renombre de clústeres mapea los clústeres usados por las instrucciones de distintos hilos en clústeres físicos diferentes para reducir los conflictos y minimizar la infrautilización de recursos. También se proponen: un híbrido entre CSMT y IMT que permite aumentar el número de hilos soportados, combinado de instrucciones heterogéneo donde algunas instrucciones se combinan usando SMT y el resto CSMT, y finalmente, ¿split-issue¿, una técnica que permite lanzar una instrucción parcialmente lo que facilita que se pueda combinar con otras.

    Very Long Instruction Word (VLIW) processors are very popular in embedded and mobile computing domain. Use of VLIW processors range from Digital Signal Processors (DSPs) found in a plethora of communication and multimedia devices to Graphics Processing Units (GPUs) used in gaming and high performance computing devices. The advantage of VLIWs is their low complexity and low power design which enable high performance at a low cost. Scalability of VLIWs is limited by the scalability of register file ports. It is not viable to have a VLIW processor with a single large register file because of area and power consumption implications of the register file. Clustered VLIW solve the register file scalability issue by partitioning the register file into multiple clusters and a set of functional units that are attached to register file of that cluster. Using a clustered approach, higher issue width can be achieved while keeping the cost of register file within reasonable limits. Several commercial VLIW processors have been designed using the clustered VLIW model. VLIW processors can be used to run a larger set of applications. Many of these applications have a good Lnstruction Level Parallelism (ILP) which can be efficiently utilized. However, several applications, specially the ones that are control code dominated do not exibit good ILP and the processor is underutilized. Cache misses is another major source of resource underutiliztion. Multithreading is a popular technique to improve processor utilization. Interleaved MultiThreading (IMT) hides cache miss latencies by scheduling a different thread each cycle but cannot hide unused instructions slots. Simultaneous MultiThread (SMT) can also remove ILP under-utilization by issuing multiple threads to fill the empty instruction slots. However, SMT has a higher implementation cost than IMT. The thesis presents Cluster-level Simultaneous MultiThreading (CSMT) that supports a limited form of SMT where VLIW instructions from different threads are merged at a cluster-level granularity. This lowers the hardware implementation cost to a level comparable to the cheap IMT technique. The more complex SMT combines VLIW instructions at the individual operation-level granularity which is quite expensive especially in for a mobile solution. We refer to SMT at operation-level as OpSMT to reduce ambiguity. While previous studies restricted OpSMT on a VLIW to 2 threads, CSMT has a better scalability and upto 8 threads can be supported at a reasonable cost. The thesis proposes several other techniques to further improve CSMT performance. In particular, Cluster renaming remaps the clusters used by instructions of different threads to reduce resource conflicts. Cluster renaming is quite effective in reducing the issue-slots under-utilization and significantly improves CSMT performance.The thesis also proposes: a hybrid between IMT and CSMT which increases the number of supported threads, heterogeneous instruction merging where some instructions are combined using SMT and CSMT rest, and finally, split-issue, a technique that allows to launch partially an instruction making it easier to be combined with others.

  • Aprendizaje activo basado en problemas

     Alvarez Martinez, Carlos; Fernandez Jimenez, Agustin; Llosa Espuny, Jose Francisco; Sanchez Carracedo, Fermin
    ReVisión
    Date of publication: 2013-09
    Journal article

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    Durante años, los autores del presente trabajo hemos practicado diversos métodos para fomentar el aprendizaje activo de los estudiantes a partir de la resolución de problemas, tanto en clase como fuera de ella. Los últimos cuatro cursos hemos utilizado en la clase de problemas de la asignatura una metodología que consiste en encargar a los estudiantes cada semana que resuelvan un pequeño conjunto de problemas que trabajarán en clase la semana siguiente. En clase, los juntamos en equipos de tres o cuatro personas, que discuten sus respectivas soluciones y entregan una solución de consenso al final de la clase. Esta solución se les devuelve corregida en la siguiente clase. Los resultados recopilados durante estos cuatro cursos prueban que asistir y participar activamente en clase ayuda mucho en el aprendizaje, y que trabajar y pensar los problemas antes de ir ayuda aún más, ya que permite aprovechar mejor las clases. En estos cuatro años, el 78 % de los estudiantes que realizaron al menos el 90 % de los problemas aprobaron la asignatura por controles, sin necesidad de realizar el examen final, mientras que el 64 % de los estudiantes que realizaron menos del 50 % de los problemas no consiguieron superar la asignatura.

  • Access to the full text
    Aprendizaje activo basado en problemas  Open access

     Alvarez Martinez, Carlos; Fernandez Jimenez, Agustin; Llosa Espuny, Jose Francisco; Sanchez Carracedo, Fermin
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2013-07
    Presentation of work at congresses

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    Durante años, los autores del presente trabajo hemos practicado diversos métodos para fomentar el aprendizaje activo de los estudiantes a partir de la resolución de problemas, tanto en clase como fuera de ella. Los últimos cuatro cursos hemos utilizado en clase de problemas de la asignatura una metodología que consiste en encargar a los estudiantes cada semana que resuelvan un pequeño conjunto de problemas que trabajarán en clase la semana siguiente. En clase, los juntamos en equipos de tres o cuatro personas, que discuten sus respectivas soluciones y entregan una solución de consenso al final de la clase. Esta solución se les devuelve corregida en la siguiente clase. Los resultados recopilados durante estos cuatro cursos prueban que asistir y participar activamente en clase ayuda mucho en el aprendizaje, y que trabajar y pensar los problemas antes de ir, ayuda aún más, ya que permite aprovechar mejor las clases. En estos cuatro años, el 78% de los estudiantes que realizaron al menos el 90% de los problemas aprobaron la asignatura por controles, sin necesidad de realizar el examen final, mientras que el 64% de los estudiantes que realizaron menos del 50% de los problemas no consiguieron superar la asignatura.

    Durante años, los autores del presente trabajo hemos practicado diversos métodos para fomentar el aprendizaje activo de los estudiantes a partir de la resolución de problemas, tanto en clase como fuera de ella. Los últimos cuatro cursos hemos utilizado en clase de problemas de la asignatura una metodología que consiste en encargar a los estudiantes cada semana que resuelvan un pequeño conjunto de problemas que trabajarán en clase la semana siguiente. En clase, los juntamos en equipos de tres o cuatro personas, que discuten sus respectivas soluciones y entregan una solución de consenso al final de la clase. Esta solución se les devuelve corregida en la siguiente clase. Los resultados recopilados durante estos cuatro cursos prueban que asistir y participar activamente en clase ayuda mucho en el aprendizaje, y que trabajar y pensar los problemas antes de ir, ayuda aún más, ya que permite aprovechar mejor las clases. En estos cuatro años, el 78% de los estudiantes que realizaron al menos el 90% de los problemas aprobaron la asignatura por controles, sin necesidad de realizar el examen final, mientras que el 64% de los estudiantes que realizaron menos del 50% de los problemas no consiguieron superar la asignatura.

  • Uso de mandos interactivos para la evaluación formativa con realimentación rápida

     Alvarez Martinez, Carlos; Llosa Espuny, Jose Francisco
    ReVisión
    Date of publication: 2010-10
    Journal article

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  • CSMT: Simultaneous Multithreading for Clustered VLIW Processors

     Gupta, Manoj; Sanchez Carracedo, Fermin; Llosa Espuny, Jose Francisco
    IEEE transactions on computers
    Date of publication: 2010-03
    Journal article

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  • Evaluación formativa con feedback rápido usando mandos interactivos

     Alvarez Martinez, Carlos; Llosa Espuny, Jose Francisco
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2010-07
    Presentation of work at congresses

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  • Access to the full text
    A low cost split-issue technique to improve performance of SMT clustered VLIW processors  Open access

     Gupta, Manoj; Sanchez Carracedo, Fermin; Llosa Espuny, Jose Francisco
    IEEE International Parallel and Distributed Processing Symposium
    Presentation's date: 2010-04
    Presentation of work at congresses

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    Abstract—Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreading (SMT) is a popular technique for improving processor performance. To maintain execution semantics, a VLIW instruction needs to be issued in entirety, which restricts the opportunities in SMT. Split-issue at operation-level is a technique that allows issuing a VLIW instruction in parts without breaking execution semantics. Issuing an instruction in parts allows non-conflicting part of an instruction to be issued along with other instructions and improves SMT performance. However, implementing splitissue at operation-level requires complex structures and is not practical for an embedded VLIW processor. This paper proposes cluster-level split-issue, which implements split-issue at a cluster-level boundary for clustered VLIW processors. Cluster-level split-issue has a very low hardware overhead in contrast to split-issue at operation-level. Experimental results show that cluster-level split-issue, despite being more restrictive than split-issue at operation-level, achieves similar performance and improves SMT performance significantly.

  • Mandos interactivos en EC2

     Alvarez Martinez, Carlos; Llosa Espuny, Jose Francisco
    Jornades de Docència del Departament d'Arquitectura de Computadors
    Presentation's date: 2010-02
    Presentation of work at congresses

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  • ARQUITECTURA DE COMPUTADORS D'ALTRES PRESTACIONS (CAP)

     Jimenez Castells, Marta; Pericas Gleim, Miquel; Navarro Guerrero, Juan Jose; Llaberia Griño, Jose M.; Llosa Espuny, Jose Francisco; Villavieja Prados, Carlos; Alvarez Martinez, Carlos; Jimenez Gonzalez, Daniel; Ramirez Bellido, Alejandro; Morancho Llena, Enrique; Fernandez Jimenez, Agustin; Pajuelo González, Manuel Alejandro; Olive Duran, Angel; Sanchez Carracedo, Fermin; Moreto Planas, Miquel; Verdu Mula, Javier; Abella Ferrer, Jaume; Valero Cortes, Mateo
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  • Access to the full text
    Hybrid multithreading for VLIW processors  Open access

     Gupta, Manoj; Sanchez Carracedo, Fermin; Llosa Espuny, Jose Francisco
    International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
    Presentation's date: 2009-10
    Presentation of work at congresses

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    Several multithreading techniques have been proposed to reduce resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique that improves processor performance by issuing multiple instructions from di erent threads. In VLIW processors, SMT requires extra hardware to merge instructions from di erent threads. The complexity of this hardware increases substantially with the number of threads. On the other hand, techniques like Interleaved MultiThreading (IMT) do not need any merging hardware, and support a larger number of threads at reasonable cost. In this paper, we propose Hybrid MultiThreading (HMT), a technique that at each cycle merges instructions from only a subset of threads. HMT supports a reasonable number of threads with a low merging hardware cost. For instance, it is possible to support 8 hardware threads with a merging hardware for only 2 threads. The experimental results show that using HMT improves the multithreading performance significantly. Further, supporting 8 hardware threads with HMT but using a 4-thread merging hardware achieves a performance similar to merging 8 threads simultaneously with a significantly lower merging hardware cost.

    © ACM, 2009. This is the author's version of the work: http://doi.acm.org/10.1145/1629395.1629403

    Postprint (author’s final draft)

  • Thread merging schemes for multithreaded clustered VLIW processors

     Gupta, Manoj; Sanchez Carracedo, Fermin; Llosa Espuny, Jose Francisco
    International Conference on Parallel Processing
    Presentation's date: 2009-09
    Presentation of work at congresses

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  • Power-efficient VLIW design using clustering and widening

     Pericas Gleim, Miquel; Ayguade Parra, Eduard; Zalamea, Javier; Valero Cortes, Mateo; Llosa Espuny, Jose Francisco
    International Journal of Embedded Systems
    Date of publication: 2008-10
    Journal article

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  • Incorporació de sistemas de resposta interactiva a la docència presencial

     Llosa Espuny, Jose Francisco; Sanchez Carracedo, Fermin; Alvarez Martinez, Carlos; Fonseca Casas, Pau; Delgado Mercé, Jaime; Sese Castel, Gemma; Llorente Viejo, Silvia
    Participation in a competitive project

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  • Estrategias para el diseño de laboratorios orientados al aprendizaje continuo

     Llosa Espuny, Jose Francisco
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2008-07-09
    Presentation of work at congresses

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  • Estrategias para el diseño de laboratorios orientados al aprendizaje continuo

     Fernandez Jimenez, Agustin; Llosa Espuny, Jose Francisco; Sanchez Carracedo, Fermin
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2008-07
    Presentation of work at congresses

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  • Merge Logic for Clustered Multithreaded VLIW Processors

     Manoj, Gupta; Sanchez Carracedo, Fermin; Llosa Espuny, Jose Francisco
    10th Euromicro Conference on Digital Systems Design: Architectures, Methods and Tools (DSD 2007)
    Presentation of work at congresses

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  • Performance evaluation of CSMT for VLIW processors

     Gupta, Manoj; Sanchez Carracedo, Fermin; Llosa Espuny, Jose Francisco
    International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
    Presentation's date: 2007-07
    Presentation of work at congresses

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  • Cluster-Level Simultaneous Multithreading for VLIW Processors

     Manoj, Gupta; Sanchez Carracedo, Fermin; Llosa Espuny, Jose Francisco
    25th IEEE International Conference on Computer Design, ICCD 2007
    Presentation's date: 2007-10
    Presentation of work at congresses

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  • La enseñanza de Estructura de Computadores en el EEES

     Sanchez Carracedo, Fermin; Fernandez Jimenez, Agustin; Llosa Espuny, Jose Francisco
    Jornadas de Enseñanza Universitaria de la Informática
    Presentation's date: 2007-07
    Presentation of work at congresses

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  • Instruction Merge Logic for Clustered Multithreaded VLIW Processors

     Manoj, Gupta; Llosa Espuny, Jose Francisco; Sanchez Carracedo, Fermin
    Date: 2007-06
    Report

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  • Performance Evaluation of Cluster-Level Simultaneous Multithreading for VLIW Processors

     Manoj, Gupta; Llosa Espuny, Jose Francisco; Sanchez Carracedo, Fermin
    Date: 2007-06
    Report

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  • Merge Logic for Clustered Multithreaded VLIW Processors

     Manoj, Gupta; Llosa Espuny, Jose Francisco; Sanchez Carracedo, Fermin
    Date: 2007-06
    Report

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  • Near-Optimal Padding for Removing Conflict Misses

     Vera Rivera, Francisco Javier; Llosa Espuny, Jose Francisco; Gonzalez Colas, Antonio Maria
    Lecture notes in computer science
    Date of publication: 2006-06
    Journal article

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  • Statistical Simulation of Large-Scale Multicomputer Systems

     Galanis ., Nikolaos; Llosa Espuny, Jose Francisco
    Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2006)
    Presentation of work at congresses

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  • Cluster Level Multithreading for VLIW Processors

     Manoj, Gupta; Llosa Espuny, Jose Francisco; Sanchez Carracedo, Fermin
    Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2006)
    Presentation's date: 2006-07
    Presentation of work at congresses

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  • Cluster Level Multithreading for VLIW Processors

     Llosa Espuny, Jose Francisco
    Second International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2006)
    Presentation's date: 2006-07-26
    Presentation of work at congresses

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  • Cluster-Level Simultaneous Multithreading for VLIW Processors

     Manoj, Gupta; Llosa Espuny, Jose Francisco; Sanchez Carracedo, Fermin
    Date: 2006-07
    Report

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  • Kilo Instruction Processors

     Cristal Kestelman, Adrian
    Defense's date: 2006-04-18
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses

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  • An Accurate Cost Model for Guiding Data Locality Transformations

     Xavier, Vera; Abella Ferrer, Jaume; Llosa Espuny, Jose Francisco; Gonzalez Colas, Antonio Maria
    ACM transactions on programming languages and systems
    Date of publication: 2005-09
    Journal article

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  • A Fast and Accurate Framework to Analyze and Optimize Cache Memory Behavior

     Xavier, Vera; Bermudo, Nerina; Llosa Espuny, Jose Francisco; Gonzalez Colas, Antonio Maria
    ACM transactions on programming languages and systems
    Date of publication: 2004-03
    Journal article

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  • High Performance Computing

     Llosa Espuny, Jose Francisco
    11 th International Conference
    Presentation's date: 2004-12-01
    Presentation of work at congresses

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  • Hipeac - European Network of Excellence on High-Performance Embedded Architecture and Compilation

     Valero Cortes, Mateo; Navarro Guerrero, Juan Jose; Gil Gómez, Maria Luisa; Ramirez Bellido, Alejandro; Llosa Espuny, Jose Francisco; Morancho Llena, Enrique; Canal Corretger, Ramon; Moreto Planas, Miquel
    Participation in a competitive project

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  • Out-of Order Commint Processors

     Llosa Espuny, Jose Francisco
    10 th International Symposium on Highn Performance Computer Architecture HPCA-10
    Presentation's date: 2004-02-15
    Presentation of work at congresses

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  • Out-of Order Commint Processors

     Cristal Kestelman, Adrian; Daniel, Ortega; JOSEP, LLOSA; Llosa Espuny, Jose Francisco; Valero Cortes, Mateo
    10 th International Symposium on Highn Performance Computer Architecture HPCA-10
    Presentation of work at congresses

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  • Register constrained Modulo Scheduling

     Zalamea Leon, Francisco Javier; Llosa Espuny, Jose Francisco; Ayguade Parra, Eduard; Valero Cortes, Mateo
    IEEE transactions on parallel and distributed systems
    Date of publication: 2004-05
    Journal article

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  • Software and Hardware Techniques to Optimize Register File Utilization in VLIW

     Zalamea Leon, Francisco Javier; Llosa Espuny, Jose Francisco; Ayguade Parra, Eduard; Valero Cortes, Mateo
    International journal of parallel programming
    Date of publication: 2004-12
    Journal article

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  • Performance and Power Evaulation of Clustered VLIW Processors with Wide Functional Units

     Pericas Gleim, Miquel; Ayguade Parra, Eduard; Zalamea Leon, Francisco Javier; Llosa Espuny, Jose Francisco; Valero Cortes, Mateo
    Lecture notes in computer science
    Date of publication: 2004-11
    Journal article

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  • Out-of-Order Commit Processors

     Cristal Kestelman, Adrián; Martínez, José F; Ortega Fernandez, Daniel; Llosa Espuny, Jose Francisco; Valero Cortes, Mateo
    Date: 2003-07
    Report

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  • A Case for Resource-conscious Out-of-order Processors

     Cristal Kestelman, Adrián; Martínez, José F; Llosa Espuny, Jose Francisco; Valero Cortes, Mateo
    Date: 2003-07
    Report

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  • Ephemeral Registers with Multicheckpointing

     Cristal Kestelman, Adrian; Martínez, Jose F; Llosa Espuny, Jose Francisco; Valero Cortes, Mateo
    Date: 2003-11
    Report

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  • Power-performance trade-offs in wide clustered VLIW cores for numerical codes

     Pericas Gleim, Miquel; Ayguade Parra, Eduard; Zalamea, J; Llosa Espuny, Jose Francisco; Valero Cortes, Mateo
    5th International Symposium on High Performance Computing (ISHPC 2003)
    Presentation of work at congresses

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  • Perfomance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units

     Llosa Espuny, Jose Francisco
    Third International Workshop on Systems, Architectures, MOdeling, and Simulation (SAMOS III)
    Presentation's date: 2003-07-21
    Presentation of work at congresses

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  • Power-performance trade-offs in wide and clustered VLIW Cores for numerical codes

     Llosa Espuny, Jose Francisco
    5th International Symposium on High Performance Computing (ISHPC 2003)
    Presentation's date: 2003-10-20
    Presentation of work at congresses

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  • Optimizing Program Locality Through CMEs and GAs

     Xavier, Vera; Abella Ferrer, Jaume; JOSEP, LLOSA; Llosa Espuny, Jose Francisco; Gonzalez Colas, Antonio Maria
    12th International Conference on Parallel Architectures and Compilation Techniques (PACT'03)
    Presentation of work at congresses

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  • Power -Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes

     Pericas Gleim, Miquel; Ayguade Parra, Eduard; Zalamea Leon, Francisco Javier; Llosa Espuny, Jose Francisco; Valero Cortes, Mateo
    5th International Symposium on High Performance Computing (ISHPC 2003)
    Presentation of work at congresses

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  • Hierarchical Clustered Register File Organization for VLIW Processors

     Zalamea Leon, Francisco Javier; JOSEP, LLOSA; Llosa Espuny, Jose Francisco; Ayguade Parra, Eduard; Valero Cortes, Mateo
    IEEE International Parallel and Distributed Processing Symposium
    Presentation of work at congresses

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  • Optimal Use of Registers in Aggressive Superscalar Processors

     Llosa Espuny, Jose Francisco
    XIV Jornadas de Paralelismo
    Presentation's date: 2003-09-15
    Presentation of work at congresses

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  • Kilo-instruction processors

     Llosa Espuny, Jose Francisco
    5th International Symposium on High Performance Computing (ISHPC 2003)
    Presentation's date: 2003-10-20
    Presentation of work at congresses

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  • Optimal Use of Registers in Aggressive Superscalar Processors

     Cristal Kestelman, Adrian; Martínez, José F; JOSEP, LLOSA; Llosa Espuny, Jose Francisco; Valero Cortes, Mateo
    XIV Jornadas de Paralelismo
    Presentation of work at congresses

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  • Performance and Power Evaluation of Clustered WLIW Processors with Wide Functional Units

     Pericas Gleim, Miquel; Ayguade Parra, Eduard; Zalamea Leon, Francisco Javier; JOSEP, LLOSA; Llosa Espuny, Jose Francisco; Valero Cortes, Mateo
    Third International Workshop on Systems, Architectures, MOdeling, and Simulation (SAMOS III)
    Presentation of work at congresses

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