Go to the content (press return)

Manich Bou, Salvador

Total activity: 114
Areas of expertise
Hardware Security of ICs, IC digital design, Low power digital design, Test of ICs
Professional category
University lecturer
Doctoral courses
Enginyer Industrial
University degree
Enginyer Industrial
Research group
CRNE - Centre for Research in Nanoengineering
QINE - Low Power Design, Test, Verification and Security ICs
Department
Department of Electronic Engineering
School
Barcelona School of Industrial Engineering (ETSEIB)
E-mail
salvador.manichupc.edu
Contact details
UPC directory Open in new window
Orcid
0000-0001-5265-1209 Open in new window
Collaborative networks
 

Scientific and technological production

1 to 50 of 114 results
 
  • Circuits and Systems

     Manich, S.
    Collaboration in journals
  • Revisor. IET circuits, devices and systems

     Manich, S.
    Collaboration in journals
  • Backside polishing detector: a new protection against backside attacks  Open access

     Manich, S.; Arumi, D.; Rodriguez, R.; Mujal, J.; Hernandez, D.
    Conference on Design of Circuits and Integrated Systems
    p. 1-6
    Presentation's date: 2015-11-25
    Presentation of work at congresses
    Access to the full text
  • Defeating simple power analysis attacks in cache memories

     Neagu, M.; Manich, S.; Miclea, L.
    Conference on Design of Circuits and Integrated Systems
    p. 1-6
    DOI: 10.1109/DCIS.2015.7388557
    Presentation's date: 2015-11-25
    Presentation of work at congresses
  • Modeling and analyzing bistable ring based PUFs

     Hesselbarth, R.; Manich, S.; Sigl, G.
    Workshop on Secure Hardware and Security Evaluation
    p. 127-139
    Presentation's date: 2015-09-17
    Presentation of work at congresses
  • Improving security in cache memory by power efficient scrambling technique

     Neagu, M.; Miclea, L.; Manich, S.
    IET computers and digital techniques
    p. 1-10
    DOI: 10.1049/iet-cdt.2014.0030
    Date of publication: 2015-04-08
    Journal article
  • On the use of error detecting and correcting codes to boost security in caches against side channel attacks  Open access

     Neagu, M.; Miclea, L.; Manich, S.
    Workshop on Secure Hardware and Security Evaluation
    p. 1-6
    Presentation's date: 2015-03-13
    Presentation of work at congresses
    Access to the full text
  • Defeating microprobing attacks using a resource efficient detection circuit  Open access

     Weiner, M.; Manich, S.; Sigl, G.
    Conference on Design of Circuits and Integrated Systems
    p. 1-6
    Presentation's date: 2014-11-27
    Presentation of work at congresses
    Access to the full text
  • A low area probing detector for power efficient security ICs

     Weiner, M.; Manich, S.; Sigl, G.
    International Workshop on RFID Security
    p. 185-197
    Presentation's date: 2014-07-22
    Presentation of work at congresses
  • A low area probing detector for security IC's

     Weiner, M.; Manich, S.; Sigl, G.
    Workshop on Secure Hardware and Security Evaluation
    p. 1-6
    Presentation's date: 2014-05-30
    Presentation of work at congresses
  • Interleaved scrambling technique: A novel low-power security layer for cache memories

     Neagu, M.; Manich, S.; Miclea, L.
    IEEE European Test Symposium
    p. 1-2
    DOI: 10.1109/ETS.2014.6847844
    Presentation's date: 2014-05-29
    Presentation of work at congresses
  • Análisis y técnicas de mejora de la robustez y seguridad de circuitos nanométricos en presencia de ataques, defectos, variabilidad y Aging

     Balado, L.; Rius, J.; Manich, S.; Lamaison, R.; Renovell, M.; Lupon, E.; Arumi, D.; Rodriguez, R.
    Competitive project
  • Backside polishing detector

     Manich, S.; Arumi, D.; Rodriguez, R.; Sigl, G.; Mujal, J.
    Workshop on Secure Hardware and Security Evaluation
    Presentation's date: 2013-12-13
    Presentation of work at congresses
  • Information Leakage Reduction at the Scan-Path Output

     Manich, S.; Wamser, M. S.; Sigl, G.
    Conference on Design of Circuits and Integrated Systems
    p. 1-6
    Presentation's date: 2013-11-28
    Presentation of work at congresses
  • Differential scan-path: A novel solution for secure design-for-testability

     Manich, S.; Wamser, M. S.; Guillen, O.; Sigl, G.
    IEEE International Test Conference
    p. 1-9
    DOI: 10.1109/TEST.2013.6651902
    Presentation's date: 2013-09-11
    Presentation of work at congresses
  • A Highly time sensitive XOR gate for probe attempt detectors

     Manich, S.; Strasser, M.
    IEEE transactions on circuits and systems II: express briefs
    DOI: 10.1109/TCSII.2013.2278126
    Date of publication: 2013-09-05
    Journal article
  • Improving the security of scan path test using differential chains

     Manich, S.; Wamser, M. S.; Sigl, G.
    Workshop on Secure Hardware and Security Evaluation
    Presentation's date: 2013-05-31
    Presentation of work at congresses
  • Detection of probing attempts in secure ICs

     Manich, S.; Wamser, M. S.; Sigl, G.
    IEEE International Symposium on Hardware-Oriented Security and Trust
    p. 134-139
    DOI: 10.1109/HST.2012.6224333
    Presentation's date: 2012-06-05
    Presentation of work at congresses
  • Impacto de la variabilidad en las estrategias de test y diagnóstico de circuitos micro/nanoelectrónicos

     Balado, L.; Sanahuja, R.; Lupon, E.; Rius, J.; Rodriguez, R.; Manich, S.; Vatajelu, E.; Arumi, D.; Figueras, J.
    Competitive project
  • Defective Behaviour of an 8T SRAM Cell with Open Defects

     Rodriguez, R.; Arumi, D.; Manich, S.; Figueras, J.; Stefano Di Carlo; Paolo Prinetto; Scionti, A.
    International Conference on Advances in System Testing and Validation Lifecycle
    p. 81-86
    DOI: 10.1109/VALID.2010.19
    Presentation's date: 2010-08-24
    Presentation of work at congresses
  • Design and implementation of automatic test equipment IP module

     Fransi, S.; Farre, G.; Deiros, L. G.; Manich, S.
    IEEE European Test Symposium
    p. 244
    Presentation's date: 2010-05-25
    Presentation of work at congresses
  • HI2008-0041 Acción integrada de investigación científica y tecnológica entre España e Italia

     Arumi, D.; Rodriguez, R.; Figueras, J.; Manich, S.
    Competitive project
  • Qualitat en Electrònica: Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades

     Figueras, J.; Carrasco, J.; Lupon, E.; Manich, S.; Rodriguez, R.; Rius, J.; Balado, L.; Ferre, A.; Suñe, V.; Arumi, D.; Sanahuja, R.
    Competitive project
  • PREMIS PFC CURS 2007-2008

     Manich, S.
    Award or recognition
  • Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources

     Manich, S.; Garcia-Deiros, L.; Figueras, J.
    IEEE transactions on computer-aided design of integrated circuits and systems
    Vol. 26, num. 11, p. 2046-2058
    Date of publication: 2007-11
    Journal article
  • TEC2007-66672 DIAGNOSTICO EN TECNOLOGIAS CMOS NANOMETRICAS: MEJORA DEL RENDIMIENTO

     Arumi, D.; Rodriguez, R.; Lupon, E.; Manich, S.; Rius, J.; Balado, L.
    Competitive project
  • Computer. Aided design

     Manich, S.
    Collaboration in journals
  • IET computers and digital techniques

     Manich, S.
    Collaboration in journals
  • Dispositivo de control de la tensión de polarización de un módulo electrónico funcional

     Figueras, J.; Balado, L.; Manich, S.; Ferre, A.; Sanahuja, R.
    Date of request: 2007-07-30
    Invention patent
  • Journal of electronic testing. Theory and applications

     Manich, S.
    Collaboration in journals
  • Caracterización eléctrica de planos de tintas conductoras sobre tejidos: modelo y datos experimentales.

     Rius, J.; Palacín, M.; Casadevall, V.; Rodriguez, R.; Manich, S.; Ridao, M.
    Date: 2007-06
    Report
  • Journal of electronic testing. Theory and applications

     Manich, S.
    Collaboration in journals
  • Journal of low power electronics

     Manich, S.
    Collaboration in journals
  • Validación del ancho de banda de las líneas de transmissión textiles M133 a M137

     Manich, S.; Rius, J.; Rodriguez, R.; Casadevall, V.; Ridao, M.
    Date: 2007-02
    Report
  • Electrical Characterization of Conductive Ink Layers on Textile Fabrics: Model and Experimental Results

     Rius, J.; Manich, S.; Rodriguez, R.; Ridao, M.
    XXII Conference of Circuits and Integrated Systems
    p. 1-6
    Presentation of work at congresses
  • Low cost estimation of leakage power consumption in large nanometric CMOS circuits

     Mendoza, R.; Sanahuja, R.; Ferré, R.; Manich, S.; Balado, L.; Figueras, J.
    XXII Conference of Circuits and Integrated Systems
    Presentation of work at congresses