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    On the use of error detecting and correcting codes to boost security in caches against side channel attacks  Open access

     Neagu, Madalin; Miclea, Liviu; Manich Bou, Salvador
    Workshop on Trustworthy Manufacturing and Utilization of Secure Devices
    p. 1-6
    Presentation's date: 2015-03-13
    Presentation of work at congresses

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    Microprocessor memory is sensitive to cold boot attacks. In this kind of attacks, memory remanence is exploited to download its content after the microprocessor has been struck by a hard boot. If just in this moment, a crypto-algorithm was in execution, the memory data can be downloaded into a backup memory and specialized tools can be used to extract the secret keys. In the main memory data can be protected using efficient encryption techniques but in caches this is not possible unless the performance becomes seriously degraded. Recently, an interleaved scrambling technique (IST) was presented to improve the security of caches against cold boot attacks. While IST is effective for this particular kind of attacks, a weakness exists against side channel attacks, in particular using power analysis. Reliability of data in caches is warranted by means of error detecting and correcting codes. In this work it is shown how these kinds of codes can be used not only to improve reliability but also the security of data. In particular, a self-healing technique is selected to make the IST technique robust against side channel attacks using power analysis.

    Postprint (author’s final draft)

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    Defeating microprobing attacks using a resource efficient detection circuit  Open access

     Weiner, Michael; Manich Bou, Salvador; Sigl, Georg
    Conference on Design of Circuits and Integrated Systems
    p. 1-6
    Presentation's date: 2014-11-27
    Presentation of work at congresses

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    Microprobing is an attack technique against integrated circuits implementing security functions, such as OTP tokens or smartcards. It allows intercepting secrets from onchip wires as well as injecting faults for other attacks. While the necessity to etch open chip packages and to remove the passivation layer makes microprobing appear expensive, it was shown that a successful attack can be run with equipment worth a few thousand euros. On the protector’s side, however, appropriate countermeasures such as active shields, redundancy of core components, or analog detection circuits containing large capacitors, are still expensive. We present a resource efficient microbing detection circuit that we call Low Area Probing Detector (LAPD). It measures minimal timing differences between on-chip wires caused by the capacitive load of microprobes. Simulations show that it can detect up-todate probes with capacitances as low as 10 fF. As a novelty, the LAPD is merely based on digital components and does not require analog circuitry, which reduces the required area and process steps compared to previous approaches.

    Postprint (author’s final draft)

  • A low area probing detector for power efficient security ICs

     Weiner, Michael; Manich Bou, Salvador; Sigl, Georg
    International Workshop on RFID Security
    p. 185-197
    Presentation's date: 2014-07-22
    Presentation of work at congresses

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    In this paper, a low cost, Low Area Probing Detector (LAPD) is presented. Probing or microprobing is an attack technique against integrated circuits implementing security functions, such as OTP tokens or smartcards. It allows intercepting secrets from on-chip wires as well as injecting faults for other attacks. Microprobing is invasive as classied by Skorobogatov in 2005 and requires opening the microchip package as well as removing the passivation layer. While it may sound complicated and expensive, Maier and Nohl showed in 2012 that microprobing is feasible for low-budget adversaries. However, existing protection techniques against microprobing, such as active shields, redundancy of core components, or analog detection circuits containing large capacitors, are still expensive. The LAPD provides low-cost protection against microprobing. It measures minimal timing dierences between on-chip wires caused by the capacitive load of microprobes. As a novelty, it is merely based on digital components and does not require analog circuitry, which reduces the required area and process steps compared to previous approaches. Simulations show that the LAPD can detect up-to-date probes with capacitances as low as 10 fF.

    In this paper, a low cost, Low Area Probing Detector (LAPD) is presented. Probing or microprobing is an attack technique against integrated circuits implementing security functions, such as OTP tokens or smartcards. It allows intercepting secrets from on-chip wires as well as injecting faults for other attacks. Microprobing is invasive as classi ed by Skorobogatov in 2005 and requires opening the microchip package as well as removing the passivation layer. While it may sound complicated and expensive, Maier and Nohl showed in 2012 that microprobing is feasible for low-budget adversaries. However, existing protection techniques against microprobing, such as active shields, redundancy of core components, or analog detection circuits containing large capacitors, are still expensive. The LAPD provides low-cost protection against microprobing. It measures minimal timing di erences between on-chip wires caused by the capacitive load of microprobes. As a novelty, it is merely based on digital components and does not require analog circuitry, which reduces the required area and process steps compared to previous approaches. Simulations show that the LAPD can detect up-to-date probes with capacitances as low as 10 fF.

    Postprint (author’s final draft)

  • A low area probing detector for security IC's

     Weiner, Michael; Manich Bou, Salvador; Sigl, Georg
    Workshop on Trustworthy Manufacturing and Utilization of Secure Devices
    p. 1-6
    Presentation's date: 2014-05-30
    Presentation of work at congresses

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    In this paper, a low cost, Low Area Probing Detector (LAPD) is presented. Probing or microprobing is an attack technique against integrated circuits implementing security functions, such as OTP tokens or smartcards. It allows intercepting secrets from on-chip wires as well as injecting faults for other attacks. Microprobing is invasive as classied by Skorobogatov in 2005 and requires opening the microchip package as well as removing the passivation layer. While it may sound complicated and expensive, Maier and Nohl showed in 2012 that microprobing is feasible for low-budget adversaries. However, existing protection techniques against microprobing, such as active shields, redundancy of core components, or analog detection circuits containing large capacitors, are still expensive. The LAPD provides low-cost protection against microprobing. It measures minimal timing dierences between on-chip wires caused by the capacitive load of microprobes. As a novelty, it is merely based on digital components and does not require analog circuitry, which reduces the required area and process steps compared to previous approaches. Simulations show that the LAPD can detect up-to-date probes with capacitances as low as 10 fF.

    In this paper, a low cost, Low Area Probing Detector (LAPD) is presented. Probing or microprobing is an attack technique against integrated circuits implementing security functions, such as OTP tokens or smartcards. It allows intercepting secrets from on-chip wires as well as injecting faults for other attacks. Microprobing is invasive as classi ed by Skorobogatov in 2005 and requires opening the microchip package as well as removing the passivation layer. While it may sound complicated and expensive, Maier and Nohl showed in 2012 that microprobing is feasible for low-budget adversaries. However, existing protection techniques against microprobing, such as active shields, redundancy of core components, or analog detection circuits containing large capacitors, are still expensive. The LAPD provides low-cost protection against microprobing. It measures minimal timing di erences between on-chip wires caused by the capacitive load of microprobes. As a novelty, it is merely based on digital components and does not require analog circuitry, which reduces the required area and process steps compared to previous approaches. Simulations show that the LAPD can detect up-to-date probes with capacitances as low as 10 fF.

  • Interleaved scrambling technique: A novel low-power security layer for cache memories

     Neagu, Madalin; Manich Bou, Salvador; Miclea, Liviu
    IEEE European Test Symposium
    p. 1-2
    DOI: 10.1109/ETS.2014.6847844
    Presentation's date: 2014-05-29
    Presentation of work at congresses

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    Memory systems security has increased over the last decade due to the sensitive information which is stored in plain text. Device specific attacks, such as cold-boot and sidechannel monitoring have been reported as being successfully in retrieving encryption and private keys from algorithms like AES and RSA. In this paper, we propose a new technique of securing the cache memories by scrambling the stored data that uses interleaved scrambling vectors which reduce the power consumption if compared to the standard scrambling technique. Dissemination rules for the retained data in the cache are employed, in order to make data unusable if retrieved successfully by any type of attack. The proposed technique is analyzed and evaluated from several points of views, including area overhead, power consumption and time performance.

  • Análisis y técnicas de mejora de la robustez y seguridad de circuitos nanométricos en presencia de ataques, defectos, variabilidad y aging

     Balado Suarez, Luz Maria; Rius Vázquez, Josep; Manich Bou, Salvador; Lamaison Urioste, Rafael Martin; Renovell, Michel; Lupon Roses, Emilio Jose; Rodríguez Montañés, Rosa
    Competitive project

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  • Backside polishing detector

     Manich Bou, Salvador; Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Sigl, Georg; Mujal, Jordi
    Workshop on Trustworthy Manufacturing and Utilization of Secure Devices
    Presentation's date: 2013-12-13
    Presentation of work at congresses

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    Present techniques for attacking secure devices include chip backside reverse engineering. In this presentation a detector sensitive to the removal of silicon backside material is presented. It is based on the side effect of the through silicon bias used for high bandwith communication through silicon die in digital chips.

  • Information Leakage Reduction at the Scan-Path Output

     Manich Bou, Salvador; Wamser, Markus S.; Sigl, Georg
    Conference on Design of Circuits and Integrated Systems
    p. 1-6
    Presentation's date: 2013-11-28
    Presentation of work at congresses

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    In this paper we present a new scan-path structure for improving the security of systems including a scan path, which normally introduces a security critical information channel into a design. The structure, named differential scan path (DiSP), divides the internal state of the scan path into two sections. During shift-out operation, only subtraction of the two sections is provided. The discovery of the internal state from this subtraction requires guesswork that increases exponentially with scan path length. Subtraction does not preserve parity, a property sometimes used during attacks. Output subtraction cannot be reversed and hence it is not possible to restore the internal state of the chip from the output. The structure is simple, requires little area and no unlocking keys.

    In this paper we present a new scan-path structure for improving the security of systems including a scan path, which normally introduces a security critical information channel into a design. The structure, named differential scan path (DiSP), divides the internal state of the scan path into two sections. During shift-out operation, only subtraction of the two sections is provided. The discovery of the internal state from this subtraction requires guesswork that increases exponentially with scan path length. Subtraction does not preserve parity, a property sometimes used during attacks. Output subtraction cannot be reversed and hence it is not possible to restore the internal state of the chip from the output. The structure is simple, requires little area and no unlocking keys.

  • Differential scan-path: A novel solution for secure design-for-testability

     Manich Bou, Salvador; Wamser, Markus S.; Guillen, Oscar M.; Sigl, Georg
    IEEE International Test Conference
    p. 1-9
    DOI: 10.1109/TEST.2013.6651902
    Presentation's date: 2013-09-11
    Presentation of work at congresses

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    In this paper, we present a new scan-path structure for improving the security of systems including scan paths, which normally introduce a security critical information leak channel into a design. Our structure, named differential scan path (DiSP), divides the internal state of the scan path in two sections. During the shift-out operation, only subtraction of the two sections is provided. Inferring the internal state from this subtraction requires much guesswork that increases exponen-tially with scan path length while the resulting fault coverage is only marginally altered. Subtraction does not preserve parity, thus avoiding attacks using parity information. The structure is simple, needs little area and does not require unlocking keys. Through implementing the DiSP in an elliptic curve crypto-graphic coprocessor, we demonstrate how easily it can be inte-grated into existing design tools. Simulations show that test effectiveness is preserved and that the internal state is effec-tively hidden.

  • A Highly time sensitive XOR gate for probe attempt detectors

     Manich Bou, Salvador; Strasser, Martin
    IEEE transactions on circuits and systems II: express briefs
    DOI: 10.1109/TCSII.2013.2278126
    Date of publication: 2013-09-05
    Journal article

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    Probe attempt detectors are sensors designed to protect buses of secure chips against the physical contact of probes. The operation principle of these detectors relies on the comparison of the delay propagation times between lines. CMOS XOR gates are very well suited for this comparison since they are small, fast, and compatible with the technology used in secure chips. However, the lack of activity while comparing matched lines and the limited reaction time pose a risk for tampering and decrease the sensitivity of the sensor, respectively. In this brief, a modification of a CMOS XOR gate is presented, which solves both the aforementioned problems.

    Probe attempt detectors are sensors designed to protect buses of secure chips against the physical contact of probes. The operation principle of these detectors relies on the comparison of the delay propagation times between lines. CMOS XOR gates are very well suited for this comparison since they are small, fast, and compatible with the technology used in secure chips. However, the lack of activity while comparing matched lines and the limited reaction time pose a risk for tampering and decrease the sensitivity of the sensor, respectively. In this brief, a modification of a CMOS XOR gate is presented, which solves both the aforementioned problems.

  • Improving the security of scan path test using differential chains

     Manich Bou, Salvador; Wamser, Markus S.; Sigl, Georg
    Workshop on Trustworthy Manufacturing and Utilization of Secure Devices
    Presentation's date: 2013-05-31
    Presentation of work at congresses

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    In this paper we present a new scan-path structure for improving the security of systems including a scan path, which normally introduces a security critical information channel into a design. The structure, named differential scan path (DiSP), divides the internal state of the scan path into two sections. During shift-out operation, only subtraction of the two sections is provided. The discovery of the internal state from this subtraction requires guesswork that increases exponentially with scan path length. Subtraction does not preserve parity, a property sometimes used during attacks. Output subtraction cannot be reversed and hence it is not possible to restore the internal state of the chip from the output. The structure is simple, requires little area and no unlocking keys.

    In this paper we present a new scan-path structure for improving the security of systems including a scan path, which normally introduces a security critical information channel into a design. The structure, named differential scan path (DiSP), divides the internal state of the scan path into two sections. During shift-out operation, only subtraction of the two sections is provided. The discovery of the internal state from this subtraction requires guesswork that increases exponentially with scan path length. Subtraction does not preserve parity, a property sometimes used during attacks. Output subtraction cannot be reversed and hence it is not possible to restore the internal state of the chip from the output. The structure is simple, requires little area and no unlocking keys.

  • Detection of probing attempts in secure ICs

     Manich Bou, Salvador; Wamser, Markus S.; Sigl, Georg
    IEEE International Symposium on Hardware-Oriented Security and Trust
    p. 134-139
    DOI: 10.1109/HST.2012.6224333
    Presentation's date: 2012-06-05
    Presentation of work at congresses

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  • DISPOSITIVO DE CONTROL DINÁMICO DE ILUMINACIÓN EN ESPACIOS CERRADOS PARA OPTIMIZAR Y REDUCIR EL CONSUMO ENERGÉTICO

     Manich Bou, Salvador; Caballero Díaz, Luis
    Date of request: 2011-06-29
    Invention patent

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    Dispositivo de control dinámico de iluminación en espacios cerrados para optimizar y reducir el consumo energético, que comprende unidad de control central (5) con procesador, unidades de control local (2) conectadas a sensores de luz (1) asociados a las fuentes de luz (3) para transmitir información hacia la unidad de control central y transmitir sus consignas hacia las fuentes de luz; y sensores de posición (4). Una unidad de control de posición (6) gestiona múltiples sensores de posición (4), sirviendo de enlace con la unidad de control central (5) comunicándose mediante bus de datos. Los sensores de posición (4) son activos, pasivos o virtuales, constituidos por dispositivos que se pueden o no llevar encima con comunicación por radio con la unidad de control de posición (6) o directamente con la unidad de control central (5) y que permiten modificar o no el nivel óptimo de iluminación deseado.

  • Impacto de la variabilidad en las estrategias de test y diagnóstico de circuitos micro/nanoelectrónicos

     Balado Suarez, Luz Maria; Sanahuja Moliner, Ricard; Lupon Roses, Emilio Jose; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Manich Bou, Salvador; Vatajelu, Elena Ioana; Arumi Delgado, Daniel; Figueras Pamies, Juan
    Competitive project

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  • Defective Behaviour of an 8T SRAM Cell with Open Defects

     Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Manich Bou, Salvador; Figueras Pamies, Juan; Di Carlo, Stefano; Prinetto, Paolo; Scionti, Alberto
    International Conference on Advances in System Testing and Validation Lifecycle
    p. 81-86
    DOI: 10.1109/VALID.2010.19
    Presentation's date: 2010-08-24
    Presentation of work at congresses

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  • Design and implementation of automatic test equipment IP module

     Fransi Palos, Sergi; Farre Lozano, Goretti; García Deiros, Lucas; Manich Bou, Salvador
    IEEE European Test Symposium
    p. 244
    Presentation's date: 2010-05-25
    Presentation of work at congresses

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    This paper presents an Intellectual Property (IP) module that includes fully functional autonomous Automatic Test Equipment (ATE). The module analyses responses from the Device Under Test (DUT) after sending test vectors to the device. Communication with the DUT is maintained through a synchronous bidirectional serial channel. The module has been designed for a fail-safe level of security, which means any single fault producing an erroneous output is detected. Several IP-ATEs can be synthesized in a single hardware platform to operate independently or coordinately.

  • IEEE transactions on circuits and systems II: express briefs

     Manich Bou, Salvador
    Collaboration in journals

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  • HI2008-0041 Acción integrada de investigación científica y tecnológica entre España e Italia

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pamies, Juan; Manich Bou, Salvador
    Competitive project

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  • Qualitat en Electrònica: Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades

     Figueras Pamies, Juan; Carrasco Lopez, Juan Antonio; Lupon Roses, Emilio Jose; Manich Bou, Salvador; Rodríguez Montañés, Rosa; Rius Vazquez, Jose; Balado Suarez, Luz Maria; Ferre Fabregas, Antoni; Suñe Socias, Victor Manuel; Arumi Delgado, Daniel; Sanahuja Moliner, Ricard
    Competitive project

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  • Análisis de la respuesta de los sensores de presión textiles pes-0, pes-4 y pes-8

     Manich Bou, Salvador; Rius Casals, Juan-manuel; Casadevall, V; Ridao, M
    Date: 2008-04
    Report

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  • PREMIS PFC CURS 2007-2008

     Manich Bou, Salvador
    Award or recognition

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  • IEEE transactions on circuits and systems II: express briefs

     Manich Bou, Salvador
    Collaboration in journals

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  • Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources

     Manich Bou, Salvador; Garcia-Deiros, L; Figueras Pamies, Juan
    IEEE transactions on computer-aided design of integrated circuits and systems
    Vol. 26, num. 11, p. 2046-2058
    Date of publication: 2007-11
    Journal article

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  • Computer. Aided design

     Manich Bou, Salvador
    Collaboration in journals

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  • TEC2007-66672 DIAGNOSTICO EN TECNOLOGIAS CMOS NANOMETRICAS: MEJORA DEL RENDIMIENTO

     Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Lupon Roses, Emilio Jose; Manich Bou, Salvador; Rius Vazquez, Jose; Balado Suarez, Luz Maria
    Competitive project

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  • IET computers and digital techniques

     Manich Bou, Salvador
    Collaboration in journals

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  • Dispositivo de control de la tensión de polarización de un módulo electrónico funcional

     Figueras Pamies, Juan; Balado Suarez, Luz Maria; Manich Bou, Salvador; Ferre Fabregas, Antoni; Sanahuja Moliner, Ricard
    Date of request: 2007-07-30
    Invention patent

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    Dispositivo de control de la tensión de polarización de un módulo electrónico funcional.

    Dispositivo de control de la tensión de polarización (VDD-VS) para minimizar la potencia consumida por un módulo electrónico funcional (1) garantizando la retención de memoria, que comprende un conjunto de transistores (2) conectado en serie, un registro de control digital (3) que actúa sobre ellos mediante el control de su tensión de puerta (4), una unidad de medida (5) de la corriente de fuga y una unidad de control (3) que a partir de las señales de medida generadas por la unidad de medida (5) genera los valores digitales del registro de control para que la intersección entre la curva de carga del módulo y la curva de transferencia del conjunto de transistores se sitúa en la mínima corriente de fuga que mantiene la tensión de polarización (VDD-VS) por encima de una mínima tensión de polarización (U).

  • Caracterización de la respuesta estática del proceso de impresión de pistas conductoras por serigrafía en función de la anchura y espaciado entre líneas

     Rodríguez Montañés, Rosa; Casadevall, V; Rius Vazquez, Jose; Manich Bou, Salvador; Ridao Granado, Miguel
    Date: 2007-06
    Report

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  • Caracterización eléctrica de planos de tintas conductoras sobre tejidos: modelo y datos experimentales.

     Rius Vazquez, Jose; Palacín, M; Casadevall, V; Rodríguez Montañés, Rosa; Manich Bou, Salvador; Ridao Granado, Miguel
    Date: 2007-06
    Report

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  • Journal of electronic testing. Theory and applications

     Manich Bou, Salvador
    Collaboration in journals

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  • IEEE transactions on circuits and systems II: express briefs

     Manich Bou, Salvador
    Collaboration in journals

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  • Journal of electronic testing. Theory and applications

     Manich Bou, Salvador
    Collaboration in journals

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  • Journal of low power electronics

     Manich Bou, Salvador
    Collaboration in journals

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  • Validación del ancho de banda de las líneas de transmissión textiles M133 a M137

     Manich Bou, Salvador; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Casadevall, V; Ridao Granado, Miguel
    Date: 2007-02
    Report

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  • Análisis de la sensibilidad y estabilidad de los teclados textiles M125, M127, M129, M131

     Manich Bou, Salvador; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Casadevall, V; Ridao Granado, Miguel
    Date: 2007-02
    Report

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  • Electrical Characterization of Conductive Ink Layers on Textile Fabrics: Model and Experimental Results

     Rius Vazquez, Jose; Manich Bou, Salvador; Rodríguez Montañés, Rosa; Ridao, Miquel
    XXII Conference of Circuits and Integrated Systems
    p. 1-6
    Presentation of work at congresses

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  • Low cost estimation of leakage power consumption in large nanometric CMOS circuits

     Mendoza, R; Sanahuja Moliner, Ricard; Ferré, R; Manich Bou, Salvador; Balado Suarez, Luz Maria; Figueras Pamies, Juan
    XXII Conference of Circuits and Integrated Systems
    Presentation of work at congresses

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  • Estudio de la Calidad y Estabilidad de las Tintas A, B y C como Medio de Alimentación Elèctrica de Circuitos Integrados

     Manich Bou, Salvador; Rius Vazquez, Jose; Rodríguez Montañés, Rosa; Casadevall, V y M Ridao; Ridao Granado, Miguel
    Date: 2006-12
    Report

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  • IEEE transactions on circuits and systems II: express briefs

     Manich Bou, Salvador
    Collaboration in journals

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  • Minimizing Test Time in Arithmetic Test Pattern Generators

     Manich Bou, Salvador; Garcia, Lucas; Figueras Pamies, Juan
    Date: 2006-06
    Report

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  • Journal of low power electronics

     Manich Bou, Salvador
    Collaboration in journals

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  • Modeling data volume versus test time in arithmetic test pattern generators

     Manich Bou, Salvador; Figueras Pamies, Juan; Teixeira, M Santos I J P
    DCIS 2006 - XXI Conference on Design of Circutis and Integrated Systems
    p. 1-6
    Presentation of work at congresses

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