Go to the content (press return)

Espasa Sans, Roger

Total activity: 103

Scientific and technological production

1 to 50 of 103 results
 
  • A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization

     Roca Monfort, Jordi; Moya Del Barrio, Victor; González Rodríguez, Carlos; Escandell, Vicente; Murciego, Albert; Fernandez Jimenez, Agustin; Espasa Sans, Roger
    The visual computer
    Vol. 26, num. 6-8, p. 707-719
    DOI: 10.1007/s00371-010-0492-4
    Date of publication: 2010-06
    Journal article
  • A SIMD-efficient 14 instruction shader program for high-throughput microtriangle rasterization

     Roca Monfort, Jordi; Moya Del Barrio, Victor; Gonzalez, Carlos; Escandell, Vicente; Murciego, Albert; Fernandez Jimenez, Agustin; Espasa Sans, Roger
    Computers Graphic International Conference
    p. 707-719
    Presentation's date: 2010-06
    Presentation of work at congresses
    Image
  • L'assignatura Arquitectures de Computadors Actuals

     Espasa Sans, Roger
    Jornades de Docència del Departament d'Arquitectura de Computadors. 10 Anys de Jornades
    p. 1-10
    Presentation of work at congresses
  • El doctorat del DAC

     Gonzalez Colas, Antonio Maria; Ayguade Parra, Eduard; Espasa Sans, Roger; Garcia Vidal, Jorge; Navarro Guerrero, Juan Jose
    Jornades de Docència del Departament d'Arquitectura de Computadors. 10 Anys de Jornades
    p. 1-10
    Presentation of work at congresses
  • Workload Characterization of 3D Games

     Espasa Sans, Roger
    2006 IEEE International Symposium on Workload Characterization, IISWC-2006
    Presentation's date: 2006-10-25
    Presentation of work at congresses
  • Workload Characterization of 3D Games

     Jordi, Roca; Victor, Moya; Gonzalez Rodriguez, Carlos; Chema, Solis; Fernandez Jimenez, Agustin; Espasa Sans, Roger
    2006 IEEE International Symposium on Workload Characterization, IISWC-2006
    p. 1
    Presentation of work at congresses
  • ATTILA: A Cycle-Level Execution-Driven Simulator For Modern GPU Architectures

     Moya Del Barrio, Victor; Gonzalez Rodriguez, Carlos; Jordi, Roca; Fernandez Jimenez, Agustin; Espasa Sans, Roger
    2006 IEEE International Symposium on Performance Analysis of Systems And Software (ISPASS'06)
    p. 231-241
    Presentation of work at congresses
  • A Single (Unified) Shader GPU Microarchitecture for Embedded Systems

     Victor, Moya; Gonzalez, Carlos; Jordi, Roca; Fernandez Jimenez, Agustin; Espasa Sans, Roger
    Lecture notes in computer science
    Vol. 1, num. 1, p. 286-301
    Date of publication: 2005-11
    Journal article
  • Binary Redundancy Elimination  Open access

     Fernandez Gomez, Manel
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • A Single (Unified) Shader GPU Microarchitecture for Embedded Systems

     Victor, Moya; Gonzalez, Carlos; Jordi, Roca; Fernandez Jimenez, Agustin; Espasa Sans, Roger
    2005 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC'2005)
    p. 286-301
    Presentation of work at congresses
  • Shader Performance Analysis on a Modern GPU Architecture

     Victor, Moya; Gonzalez, Carlos; Jordi, Roca; Fernandez Jimenez, Agustin; Espasa Sans, Roger
    Annual IEEE/ACM International Symposium on Microarchitecture
    p. 355-364
    Presentation of work at congresses
  • Link-Time Path-Senitive Memory Redundancy Elimination

     Espasa Sans, Roger
    10 th International Symposium on Highn Performance Computer Architecture HPCA-10
    Presentation's date: 2004-02-15
    Presentation of work at congresses
  • Link-Time Path-sensitive Memory Redundancy Elimination

     Fernandez Gomez, Manel; Espasa Sans, Roger
    10 th International Symposium on Highn Performance Computer Architecture HPCA-10
    p. 300-309
    Presentation of work at congresses
  • Link-Time Path-Senitive Memory Redundancy Elimination

     Fernandez, Manel; Espasa Sans, Roger
    10 th International Symposium on Highn Performance Computer Architecture HPCA-10
    p. 300-309
    Presentation of work at congresses
  • Link-Time Optimization Techniques for Eliminating Conditinal Branch Redundancies

     Fernandez Gomez, Manel; Espasa Sans, Roger
    8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8) in conjunction with the IEEE 10th International Symposium on High-Performance Computer Architecture (HPCA-10)
    Presentation of work at congresses
  • A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications

     Francisca, Quintana; Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    Theory of computing systems
    Vol. 36, num. 5, p. 575-593
    Date of publication: 2003-09
    Journal article
  • Three Dimensional Memory Vectorization for High Bandwidth Media Memory Systems

     Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    Annual IEEE/ACM International Symposium on Microarchitecture
    p. 149-160
    Presentation's date: 2002-11-18
    Presentation of work at congresses
  • Tarantula: Next-generation Alpha with Vectors

     Espasa Sans, Roger
    XIII Jornadas de Paralelismo
    Presentation's date: 2002-09-09
    Presentation of work at congresses
  • N-dimensional Vector Architectures for Multimedia Applications

     Corbal San Adrian, Jesus
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Speculative Alias Analysis for Executable Code

     Fernandez, Manel; Espasa Sans, Roger
    Date: 2002-07
    Report
  • Asim: A Performance Model Framework

     Joel, Emer; Pritpal, Ahuja; Borch, Eric; Chi-Keung, Luk; Srilatha, Manne; Shubhendu, S Mukherjee; Harish, Patil; Wallace, Steven; Binkert, Nathan; Espasa Sans, Roger; Juan Hormigo, Antonio
    Computer
    Vol. 35, num. 2, p. 68-76
    Date of publication: 2002-02
    Journal article
  • Speculative Alias Analysis for Executable Code

     Fernandez, Manuel; Espasa Sans, Roger
    11th International Conference on Parallel Architectues and Compilation Techniques (PACT'02)
    p. 222-231
    Presentation of work at congresses
  • Tarantula: A Vector Extension to the Alpha Architecture

     Espasa Sans, Roger; Federico, Ardanaz; Joel, Emer; Stephen, Felix; Julio, Gago; Gramunt, Roger; Hernández, Isaac; Juan Hormigo, Antonio; Geoffrey, Lowney; Matthew, Mattina; Seznec, André
    The 29th Annual International Symposium on Computer Architecture (ISCA-2002)
    p. 281-292
    Presentation of work at congresses
  • Three-Dimensional Vector Prefetches for Media Applications

     Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    Date: 2001-11
    Report
  • Instruction-level parallelism and computer architecture

     Ayguade Parra, Eduard; Dahlgren, Fredrik; Christine, Eisenbeis; Espasa Sans, Roger; Guang, R Gao; Muller, Henk; Sakellariou, Rizos; Seznec, André
    Euro-Par
    p. 385
    DOI: 10.1007/3-540-44681-8_56
    Presentation's date: 2001-08
    Presentation of work at congresses
  • Load Redundancy Elimination on Executable Code

     Fernandez Gomez, Manel; Espasa Sans, Roger; Saumya, Debray
    Date: 2001-02
    Report
  • On the Efficiency of Reductions in u-SIMD Media Extensions

     Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    10th International Conference on Parallel Architectures and Compilation Techniques (PACT'01)
    p. 83-94
    Presentation of work at congresses
  • A Cost Effective Architecture for Vectorizable Numerical and Multimedia Applications

     Francisca, Quintana; Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    Thirteenth ACM Symposium on Parallel Algorithms and Architectures (SPAA 2001)
    p. 1
    Presentation of work at congresses
  • Load Redundancy Elimination on Executable Code

     Fernández, Manuel; Espasa Sans, Roger; Saumya, Debray
    Euro-Par
    p. 221-229
    Presentation of work at congresses
  • DLP + TLP Processors for the Next Generation of Media Workloads

     Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    Seventh International Symposium on High Performance Computer Architecture (HPCA-7)
    p. 219-228
    Presentation of work at congresses
  • Performance Analysis of a Feasible Superscalar+ Vector Architecture

     Quintana, F.; Espasa Sans, Roger; Valero Cortes, Mateo
    Jornadas de Paralelismo
    p. 6-10
    Presentation of work at congresses
  • Exploiting a New Level of DLP in Multimedia Applications

     Corbal San Adrian, Jesus; Valero Cortes, Mateo; Espasa Sans, Roger
    Annual IEEE/ACM International Symposium on Microarchitecture
    p. 72-79
    Presentation's date: 1999-11-16
    Presentation of work at congresses
  • An Evaluation of Different DLP Alternatives for the Embedded Media Domain

     Salamí San Juan, Esther; Corbal San Adrian, Jesus; Valero Cortes, Mateo; Espasa Sans, Roger
    1st Workshop on Media Processors and DSPs (MP-DSP-1) in conjunction with the 32nd Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-32)
    p. 100-109
    Presentation's date: 1999-11-15
    Presentation of work at congresses
  • MOM Instruction Set Architecture: Reference Manual

     Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    Date: 1999-10
    Report
  • Exploiting a new level of DLP with Matrix multimedia extensions

     Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    Date: 1999-10
    Report
  • A Simulation Study of Decoupled Vector Architectures

     Espasa Sans, Roger; Valero Cortes, Mateo
    Journal of supercomputing
    Vol. 14, num. 2, p. 129-152
    Date of publication: 1999-10
    Journal article
  • Registers Size Influence on Vector Architectures

     Villa, L; Espasa Sans, Roger; Valero Cortes, Mateo
    Lecture notes in computer science
    Vol. 1573, p. 439-451
    Date of publication: 1999-10
    Journal article
  • Evaluación de Arquitecturas Vectoriales Avanzadas con Registros Cortos

     Villa Vargas, Luis Alfonso
    Department of Computer Architecture, Universitat Politècnica de Catalunya
    Theses
  • Adding a vector unit to a superscalar processor

     Francisca, Quintana; Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    Date: 1999-06
    Report
  • Adding a Vector Unit to a Superscalar Processor

     Francisca, Quintana; Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    ACM International Conference on Supercomputing (ISC'99)
    p. 1-10
    Presentation of work at congresses
  • Dixie: A Retargetable Binary Instrumentation Tool

     Fernandez Gomez, Manel; Espasa Sans, Roger
    X Jornadas de Paralelismo
    p. 143-148
    Presentation of work at congresses
  • MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications

     Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    1999 ACM/IEEE Conference on Supercomputing (SC'99)
    p. 1-5
    Presentation of work at congresses
  • Dixie: A Retargetable Binary Instrumentation Tool

     Fernandez Gomez, Manel; Espasa Sans, Roger
    1st Workshop on Binary Translation
    p. 1-9
    Presentation of work at congresses
  • Command Vector Memory Systems: High Performance at Low Cost

     Corbal San Adrian, Jesus; Espasa Sans, Roger; Valero Cortes, Mateo
    Date: 1999-01
    Report
  • A Comparison between Superescalar and Vector Processors

     Francisca, Quintana; Espasa Sans, Roger; Valero Cortes, Mateo
    Lecture notes in computer science
    Vol. 1573, p. 548-560
    Date of publication: 1999-01
    Journal article
  • Dixie: A Retargetable Binary Instrumentation Tool

     Fernandez Gomez, Manel; Ramirez Bellido, Alejandro; Cernuda, S; Espasa Sans, Roger
    Date: 1998-12
    Report