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1 to 50 of 109 results
  • Measurements of process variability in 40-nm regular and nonregular layouts

     Mauricio Ferré, Juan; Moll Echeto, Francesc de Borja; Gomez Fernandez, Sergio
    IEEE transactions on electron devices
    Date of publication: 2014-02-01
    Journal article

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    As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a compact and 2) nonregular layout. Experimental results show a 60% reduction in variability with a cost of 60% area overhead.

  • A boolean rule-based approach for manufacturability-aware cell routing

     Cortadella Fortuny, Jordi; Petit Silvestre, Jordi; Gomez Fernandez, Sergio; Moll Echeto, Francesc de Borja
    IEEE transactions on computer-aided design of integrated circuits and systems
    Date of publication: 2014-03-01
    Journal article

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    An approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core contribution is a detailed-routing algorithm based on a Boolean formulation of the problem. The algorithm uses a novel encoding scheme, graph theory to support floating terminals, efficient heuristics to reduce the computational cost, and minimization of the number of unconnected pins in case the cell is unroutable. The versatility of the algorithm is demonstrated by routing single-and double-height cells. The efficiency is ascertained by synthesizing a library with 127 cells in about one hour and a half of CPU time. The layouts derived by the implemented tool have also been compared with the ones from a commercial library; thus, showing the competitiveness of the approach for gridded geometries.

  • Yield estimation model for lithography hotspot distortions

     Gomez Fernandez, Sergio; Moll Echeto, Francesc de Borja
    Electronics Letters
    Date of publication: 2013-08-15
    Journal article

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    A yield formulation model to estimate the amount of lithography distortion expected in a printed layout is proposed. The yield formulation relates the probability of non-failure of a lithography hotspot with the yield loss. The application of the yield model is demonstrated for three different layout configurations showing that unidimensional designs may improve manufacturing yield.

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    Systematic and random variability analysis of two different 6T-SRAM layout topologies  Open access

     Amat Bertran, Esteve; Amatlle, E.; Gomez Gonzalez, Sergio; Aymerich Capdevila, Nivard; Garcia Almudever, Carmen; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Microelectronics journal
    Date of publication: 2013-09
    Journal article

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    This paper studies the device variability influence on 6T-SRAM cells in a function of the regularity level of their layout. Systematic and random variations have been analyzed when these memory circuits are implemented on a 45 nm technology node. The NBTI aging relevance on these cells has been also studied for two layout topologies and SNM has been seen as the parameter that suffers the highest impact with respect to cell aging and variability.

  • Novel redundant logic design for noisy low voltage scenarios

     Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; García Leyva, Lancelot
    Latin American Symposium on Circuits and Systems
    Presentation's date: 2013-02
    Presentation of work at congresses

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    The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be predominant and the reliability of the future circuits will be limited. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic and functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value. Therefore, it avoids the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs with a practical full tolerance to input with a signal to noise ratio of 5dB. Turtle Logic in accordance to Kullback Leibler Distance noise immunity measurement for a NOT gate is approximately 3.6X, 13.4X and 20.9X times better than MRF, DCVS and standard CMOS techniques, respectively, when the gates are operate, with a power supply of 0.15 volts, a temperature of 100 oC and noisy inputs with Additive White Gaussian Noise with zero mean and a standard deviation of 60mV

    The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be predominant and the reliability of the future circuits will be limited. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic and functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value. Therefore, it avoids the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs with a practical full tolerance to input with a signal to noise ratio of 5dB. Turtle Logic in accordance to Kullback Leibler Distance noise immunity measurement for a NOT gate is approximately 3.6X, 13.4X and 20.9X times better than MRF, DCVS and standard CMOS techniques, respectively, when the gates are operate, with a power supply of 0.15 volts, a temperature of 100 oC and noisy inputs with Additive White Gaussian Noise with zero mean and a standard deviation of 60mV.

  • Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches

     Pouyan, Peyman; Amat Bertran, Esteve; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Design, Automation and Test in Europe
    Presentation's date: 2013-03
    Presentation of work at congresses

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    Scaling of device dimensions toward nano-scale regime has made it essential to innovate novel design techniques for improving the circuit robustness. This work proposes an implementation of adaptive proactive reconfiguration methodology that can first monitor process variability and BTI aging among 6T SRAM memory cells and then apply a recovery mechanism to extend the SRAM lifetime. Our proposed technique can extend the memory lifetime between 2X to 4.5X times with a silicon area overhead of around 10% for the monitoring units, in a 1kB 6T SRAM memory chip.

  • Logic synthesis for manufacturability considering regularity and lithography printability

     Machado, Lucas; Dal Bem, Vinicius; Moll Echeto, Francesc de Borja; Gómez Fernández, Sergio; Ribas, Renato P.; Reis, André Inacio
    IEEE Computer Society Symposium on VLSI
    Presentation's date: 2013-08
    Presentation of work at congresses

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    This paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, but it results in a significant area overhead by introducing regularity. To the best of our knowledge, this is the first approach that considers the tradeoff of cells with different levels of regularity and different area overheads during the logic synthesis, in order to improve overall design yield. A technology remapping tool with such yield model as cost function is proposed and implemented and interesting results are presented.

  • A single event transient hardening circuit design technique based on strengthening

     Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2013-08-06
    Presentation of work at congresses

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  • Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

     Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja
    IEEE International System On Chip Conference
    Presentation's date: 2012-09
    Presentation of work at congresses

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  • Evaluation of layout design styles using a quality design metric

     Gomez Fernandez, Sergio; Moll Echeto, Francesc de Borja
    IEEE International System On Chip Conference
    Presentation's date: 2012-09
    Presentation of work at congresses

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    Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecture  Open access

     Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2012-11
    Presentation of work at congresses

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  • PVTA tolerant self-adaptive clock generation architecture

     Perez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja
    International Workshop on Power and Timing Modelling and Optimization
    Presentation's date: 2012-09
    Presentation of work at congresses

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  • Layout Regularity for Design and Manufacturability  Open access

     Pons Solé, Marc
    Defense's date: 2012-10-02
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    In nowadays nanometer technology nodes, the semiconductor industry has to deal with the new challenges associated to technology scaling. On one hand, process developers face increasing manufacturing cost and variability, but also decreasing manufacturing yield. On the other hand, circuit designers and electronic design automation (EDA) developers have to reduce design turnaround time and provide the tools to cope with increasing design complexity and reduce the time-to-market. In this scenario, closer collaboration between all the actors involved is required. New approaches considering both design and manufacturing need to be explored. These are the so called design for manufacturability (DFM) techniques. A DFM trend that is becoming dominant is to make circuit layouts more regular and repetitive. The regular layout fabrics are based on the configuration of a simplied mask set, therefore reducing the manufacturing cost. Moreover, a reduced number of layout patterns is used, allowing better process variability control and optimization. Hence, regularity reduces layout complexity and therefore design complexity, allowing faster time-to-market. In this thesis, we explore forcing maximum layout regularity focusing on future technology nodes, with increasing design and manufacturability issues, where we expect layout regularity to be mandatory. With this objective, we have developed a new regular layout fabric called Via-Configurable Transistor Array (VCTA). The physical design is fully explained involving layout and geometrical considerations for transistors and interconnects. Initially, VCTA layouts developed manually have been evaluated in terms of manufacturability, but also in terms of area, energy and delay. For digital design, 32-bit binary adders designed with VCTA have been compared to standard cell layouts. For analog design, a delay-locked loop design using VCTA has been compared to its full custom version. We have also developed a physical synthesis tool that allows us to obtain VCTA circuit layouts in an automated way. Developing our own automation tool lets us controlling all the decisions made during the physical design flow to ensure that maximum layout regularity is respected. In this case the work is based on several algorithms, for instance for routing, that we have oriented to the area optimization of the layouts. Finally, in order to demonstrate the benefits of layout regularity, we have proposed a new layout regularity metric called Fixed Origin Corner Square Inspection (FOCSI). It is based on the geometrical inspection of the patterns in the layouts and it allows designers to compare regularity of designs but also how their regularity will impact their manufacturability. The FOCSI layout analysis tool can be used to optimize manufacturability.

  • A new probabilistic design methodology of nanoscale digital circuits

     García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    International Conference on Electrical Communications and Computers
    Presentation's date: 2011-02-28
    Presentation of work at congresses

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    The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is aggravated by variations caused by the difficulties of controlling Critical Dimension (CD) in nanometer technologies. The effect of variability is the difficulty in predicting and designing circuits with precise device and circuit characteristics. In this paper, a new logic design probabilistic methodology oriented to emerging and beyond CMOS in new technologies is presented, to improve tolerance to errors due to noise, defects or manufacturability errors in single gates, logic blocks or functional units. The methodology is based on the coherence of the input redundant ports using Port Redundancy (PR) and complementary redundant ports. Simulations show an excellent performance of our approach in the presence of large random noise at the inputs.

  • Monitor strategies for variability reduction considering correlation between power and timing variability

     Mauricio Ferré, Juan; Moll Echeto, Francesc de Borja; Altet Sanahujes, Josep
    IEEE International System On Chip Conference
    Presentation's date: 2011-09-27
    Presentation of work at congresses

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    As CMOS technology scales, Process, Voltage and Temperature (PVT) variations have an increasing impact on, performance and power consumption of the electronic devices. Variability causes an undesirable dispersion of performance parameters and a consequent reduction in parametric yield. Monitor and control techniques based on BB and VS can be used to reduce variability. This paper aims to determine which type of sensor provides a better overall variability reduction by taking into account the correlation between different performance magnitudes: static power, dynamic power and delay.

  • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

     Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Gonzalez Jimenez, Jose Luis; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Gonzalez Colas, Antonio Maria
    IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era
    Presentation's date: 2011-04-06
    Presentation of work at congresses

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    Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90 nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.

  • Design of complex circuits using the via-configurable transistor array regular layout fabric

     Pons Solé, Marc; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Gonzalez Colas, Antonio Maria
    IEEE International System-on-a-Chip Conference
    Presentation's date: 2011-09-26
    Presentation of work at congresses

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    Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new method for regular layout generation with Via-Configurable Transistor Arrays focusing on reducing the area overhead associated to regularity. Results for ISCAS85 benchmarks in the 45nm technology node are provided showing that comparable areas to the standard cell approach can be obtained.

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    Measuring the tolerance of self-adaptive clocks to supply voltage noise  Open access

     Perez Puigdemont, Jordi; Moll Echeto, Francesc de Borja; Cortadella Fortuny, Jordi
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2011-11-18
    Presentation of work at congresses

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    Simultaneous switching noise has become an important issue due to its signal integrity and timing implications. Therefore a lot of time and resources are spent during the PDN design to minimize the supply voltage variation. This paper presents the self-adaptive clock as an alternative to tolerate the critical path delay variation due to supply noise thanks to its self-adaptable nature. A self-adaptive clock generation circuit is proposed in this paper and its benefits, in terms of clock period reduction, are assessed under a realistic supply noise obtained through simulation for different switching activities.

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    Design guidelines towards compact litho-friendly regular cells  Open access

     Gomez Fernandez, Sergio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Elhoj, Martin; Schlinker, Guilherme; Woolaway, Nigel
    Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms
    Presentation's date: 2011-02-23
    Presentation of work at congresses

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    Transistor sizing analysis of regular fabrics  Open access

     Marranghello, Felipe S.; Dal Bem, Vinicius; Reis, André I.; Ribas, Renato P.; Moll Echeto, Francesc de Borja
    Exploiting Regularity in the Design of IPs, Architectures and Platforms
    Presentation's date: 2011-02-23
    Presentation of work at congresses

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    This paper presents an extensive transistor sizing analysis for regular transistor fabrics. Several evaluation methods have been exploited, such as DC simulations, ring oscillators and single-gate open chain structures. Different design aspects are addressed taking into account stacked transistors, cells with drive strengths and circuit critical paths. The performance degradation of using regular fabrics in comparison to standard cells is naturally expected, but it is quite important to evaluate the dimension of such impact. The results were obtained for predictive PTM45 CMOS parameters, and the conclusions can be easily extrapolated to other technology nodes and fabrication processes

  • New redundant logic design concept for high noise and low voltage scenarios

     García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gomez Fernandez, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Microelectronics journal
    Date of publication: 2011-12
    Journal article

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    This paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, where the thermal noise could be predominant and the reliability of the future circuits could be limited. The TL is a technology independent method, which aims to improve error tolerance when these errors are caused by noise within logic and functional units, sequential elements, and in general synchronous pipeline Finite State Machines. Turtle Logic operation is based on the consistency relation of redundant inputs. In the case of discrepancy, the out put of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. A two’s complement 8x8-bit pipelined Baugh–Wooley multiplier is implemented, on which several experiments reveal a perfect tolerance (0%errors) to single line discrepancies for both primary and internal nodes, with a cost of lost clock periods between 6% and 25%. The error ratio for the proposed Turtle Logic implementation with double discrepancies in both true and complementary lines are lower than 0.1% when the noise affects primary input nodes, and lower than 0.9% when the noise affects internal nodes.

  • A low-power impulse radio ultra-wideband transceiver for short-range, high-speed wireless communications

     Barajas Ojeda, Enrique
    Defense's date: 2011-08-29
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    Turtle logic: Novel IC digital probabilistic design methodology  Open access

     García Leyva, Lancelot; Rubio Sola, Jose Antonio; Moll Echeto, Francesc de Borja; Calomarde Palomino, Antonio
    Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing
    Presentation's date: 2010-10-21
    Presentation of work at congresses

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    Future electronic devices are expected to operate at lower voltage supply to save power, especially in ultimate and new technologies. The resulting reduction of logic levels approaches the thermal noise limit, and consequently signal to noise margins are reduced, exposing computations to higher soft-error rates. In other words, the future circuits will be in a scenario where all devices may fail due to soft-error produced by trend of low SNR. In order to design reliable circuits with unreliable components, novel design techniques have been introduced. The problem of designing reliable systems with unreliable components traces back to Von Neumann, who proposed the N-tuple Modular Redundancy (NMR) technique. Additional proposals have appeared in the literature addressing the problem from the point of view of noise tolerance. For instance, the approach based on Markov Random Field theory (MRF). Take in account the Hamming distance for build basic logic gates focus to high noise and low voltage scenarios. Therefore, our proposal is based on the assumption that the devices in new and future technologies will be not perfect, noisy and hence they might fail.

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    Variations-aware circuit designs for microprocessors  Open access

     Pons Solé, Marc; Moll Echeto, Francesc de Borja; Abella Ferrer, Jaume
    Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing
    Presentation's date: 2010-10-21
    Presentation of work at congresses

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    A new trend that is becoming dominant is to improve layout regularity so that the layouts to be printed are more repetitive and easy to manufacture. Our proposal is to push to the limit layout regularity to minimize manufacturing costs.

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    On evaluating temperature as observable for CMOS technology variability  Open access

     Altet Sanahujes, Josep; Gómez Salinas, Dídac; Dufis, Cédric Yvan; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    European workshop on CMOS Variability
    Presentation's date: 2010-05-26
    Presentation of work at congresses

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    The temperature at surface of a silicon die depends on the activity of the circuits placed on it. In this paper, it is analyzed how Process, Voltage and Temperature (PVT) variations affect simultaneously some figures of merit (FoM) of some digital and analog circuits and the power dissipated by such circuits. It is shown that in some cases, a strong correlation exists between the variation of the circuit FoM and the variation of the dissipated power. Since local temperature increase at the silicon surface close to the circuit linearly depends on dissipated power, the results show that temperature can be considered as an observable magnitude for CMOS technology variability monitoring.

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    VCTA: A Via-Configurable Transistor Array regular fabric  Open access

     Pons Solé, Marc; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Gonzalez Colas, Antonio Maria
    VLSI System on Chip Conference
    Presentation's date: 2010-09-28
    Presentation of work at congresses

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    Layout regularity is introduced progressively by integrated circuit manufacturers to reduce the increasing systematic process variations in the deep sub-micron era. In this paper we focus on a scenario where layout regularity must be pushed to the limit to deal with severe systematic process variations in future technology nodes. With this objective, we propose and evaluate a new regular layout style called Via-Configurable Transistor Array (VCTA) that maximizes regularity at device and interconnect levels. In order to assess VCTA maximum layout regularity tradeoffs, we implement 32-bit adders in the 90 nm technology node for VCTA and compare them with implementations that make use of standard cells. For this purpose we study the impact of photolithography proximity and coma effects on channel length variations, and the impact of shallow trench isolation mechanical stress on threshold voltage variations. We demonstrate that both variations, that are important sources of energy and delay circuit variability, are minimized through VCTA regularity.

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    Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits  Open access

     García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2010-08-05
    Presentation of work at congresses

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    As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit reliability in the presence of faults and noise. The Turtle Logic (TL) is a new probabilistic logic method based on port redundancy and complementary data, oriented to emerging and beyond CMOS technologies. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic blocks or functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs, as well as intrinsic noise (thermal noise and flicker noise) and shot noise in the power source.

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    Lithography aware regular cell design based on a predictive technology model  Open access

     Gomez Fernandez, Sergio; Moll Echeto, Francesc de Borja
    European workshop on CMOS Variability
    Presentation's date: 2010-05-27
    Presentation of work at congresses

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    As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated that layout regularity reduces the increasing impact of process variations on circuit performance and reliability. The purpose of this paper is to present the layout design of a regular cell based on 1-D elements which reduces lithography perturbations (ALARC). We depict several undesirable lithography effects and how these effects determine several layout parameters in order to achieve the required line-pattern resolution.

  • Lithography aware regular cell design based on a predictive technology model

     Gomez Fernandez, Sergio; Moll Echeto, Francesc de Borja
    Journal of low power electronics
    Date of publication: 2010-12
    Journal article

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    As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated that layout regularity reduces the increasing impact of process variations on circuit performance and reliability. The aim of this paper is to present the layout design of a regular cell based on 1-D elements which reduces lithography perturbations (ALARC). We depict several undesirable lithography effects and how these distortions determine several layout parameters in order to achieve the required line-pattern resolution. Furthermore, it is shown how the measurement of leakage power consumption based on ideal layout is not a precise metric to evaluate circuit performance, especially for low power designs. Finally, the impact of lithography patterns on delay and leakage consumption of a typical cell is provided.

  • Electronic system design paradigms in the technologies of the year 2020

     Garcia Almudever, Carmen; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    International journal of the Society of Materials Engineering for Resources.The Society of Materials Engineering for Resources of Japan
    Date of publication: 2010-10
    Journal article

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  • TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS

     Figueras Pamies, Juan; Calomarde Palomino, Antonio; Aymerich Capdevila, Nivard; Moll Echeto, Francesc de Borja; Vatajelu, Elena Ioana; Garcia Almudever, Carmen; Canal Corretger, Ramon; Pouyan, Peyman; Rubio Sola, Jose Antonio
    Participation in a competitive project

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  • ENERGY HARVESTING FROM HUMAN PASSIVE POWER.

     Mateu Saez, Maria Loreto
    Defense's date: 2009-06-05
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
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  • Modeling and design of reliable, process-variation aware nanoelectronic devices,circuits and systems

     Aragones Cervera, Xavier; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Perez Puigdemont, Jordi; Mauricio Ferré, Juan; Gómez Salinas, Dídac; Pons Solé, Marc; García Leyva, Lancelot; Gonzalez Jimenez, Jose Luis; Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja
    Participation in a competitive project

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  • GRUP DE RECERCA DE CIRCUITS I SISTEMES INTEGRATS D'ALTES PRESTACIONS (HIPICS)

     Rubio Sola, Jose Antonio; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Gonzalez Jimenez, Jose Luis; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Molina Garcia, Marc Manel; Barajas Ojeda, Enrique; Gómez Salinas, Dídac; García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Pons Solé, Marc; Trulls Fortuny, Xavier; Dufis, Cédric Yvan; Landauer, Gerhard Martin; Garcia Almudever, Carmen; Perez Puigdemont, Jordi; Aymerich Capdevila, Nivard; Gomez Fernandez, Sergio; Aragones Cervera, Xavier
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  • Modeling and design of reliable, process-variation aware nanoelectronic devices,circuits and systems

     Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Perez Puigdemont, Jordi; Mauricio Ferré, Juan; Gómez Salinas, Dídac; Pons Solé, Marc; García Leyva, Lancelot; Gonzalez Jimenez, Jose Luis; Moll Echeto, Francesc de Borja
    Participation in a competitive project

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  • SYNTHESIS USING ADVANCED PROCESS TECHNOLOGY INTEGRATED IN REGULAR CELLS, IPS, ARCHITECTURES,

     Gomez Fernandez, Sergio; Rubio Sola, Jose Antonio; Pons Solé, Marc; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Perez Puigdemont, Jordi; Moll Echeto, Francesc de Borja
    Participation in a competitive project

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  • A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs

     Andrade Miceli, Dennis Michael; Martorell, Ferran; Calomarde Palomino, Antonio; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Microelectronics journal
    Date of publication: 2009-06
    Journal article

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  • Ground bounce modelling for digital gigascale integrated circuits

     Pons, M; Martorell Cid, Ferran; Aragones Cervera, Xavier; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    International journal of electronics
    Date of publication: 2008-03
    Journal article

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  • Trade-off between on-chip decoupling capacitor and error tolerance in digital IC's under noisy environment

     Andrade, D; Martorell Cid, Ferran; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Mixed Design of Integrated Circuits and Systems
    Presentation of work at congresses

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  • Data Dependence of Delay Distribution for a Planar Bus

     Moll Echeto, Francesc de Borja; Figueras Pamies, Juan; Rubio Sola, Jose Antonio
    18th International Workshop, PATMOS 2008
    Presentation's date: 2008-09-10
    Presentation of work at congresses

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  • Access to the full text
    Error probability in synchronous digital circuits due to power supply noise  Open access

     Martorell Cid, Ferran; Pons, M; Rubio Sola, Jose Antonio; Moll Echeto, Francesc de Borja
    International Conference on Design and Test of Integrated Circuits in Nanoscale Technology
    Presentation of work at congresses

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    This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recovering techniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality.

  • Via-configurable transsitors-array:a regular design technique to improve ICs yield

     Pons, M; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera, X; Gonzalez Colas, Antonio Maria
    2nd IEEE International Workshop on Design for Manufacturability and Yield 2007
    Presentation of work at congresses

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  • Power Supply Noise and Logic Error Probability

     Martorell Cid, Ferran; Pons, M; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    European Conference on Circuit Theory and Design
    Presentation of work at congresses

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  • Voltage fluctuations in IC power supply distribution networks: impact on digital processing systems

     Andrade, D; Martorell Cid, Ferran; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    Conference on Design of Circuits and Integrated Systems
    Presentation of work at congresses

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  • Physics-based time-domain model of a magnetic induction microgenerator

     Mateu Saez, Maria Loreto; Villavieja Prados, Carlos; Moll Echeto, Francesc de Borja
    IEEE transactions on magnetics
    Date of publication: 2007-03
    Journal article

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  • Identification of micro-calorimetric devices. Part V. Basic properties for gas-solid rections

     Auguet Sangra, Carlota Eugenia; Seguin, J L; Martorell, F; Moll Echeto, Francesc de Borja; Torra Ferre, Vicenç; Lerchner, J
    Journal of thermal analysis and calorimetry
    Date of publication: 2006-11
    Journal article

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  • Designing Circuits from Imperfect Components VLSI Giga-scale Technologies

     Martorell, F; Moll Echeto, Francesc de Borja
    International journal of the Society of Materials Engineering for Resources.The Society of Materials Engineering for Resources of Japan
    Date of publication: 2006-11
    Journal article

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    Energy macro-model for on chip interconnection buses  Open access

     Mendoza, R; Pons, M; Moll Echeto, Francesc de Borja; Figueras Pamies, Juan
    Date: 2006-06
    Report

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    This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. With this model we are be able to evaluate the energy metrics for the bus under a certain traffic and information coding.

  • Power supply noise modelling for digital gigascale integrated circuits

     Pons, M; Martorell Cid, Ferran; Aragones Cervera, Xavier; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    DCIS 2006 - XXI Conference on Design of Circutis and Integrated Systems
    Presentation of work at congresses

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  • Ground bounce modelling for digital gigascale integrated circuits

     Pons, M; Martorell Cid, Ferran; Aragones Cervera, Xavier; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    IEEE DTIS 2006 International Conference on Design & Test of Integrated Systems in Nanoscale Technology
    Presentation of work at congresses

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