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1 to 50 of 149 results
  • Temperature as observable magnitude in silicon integrated circuits to characterize high frequency analog circuits

     Mateo Peña, Diego Cesar; Altet Sanahujes, Josep; Gómez Salinas, Didac; Aragones Cervera, Xavier
    International Conference on Materials Engineering for Resources
    Presentation's date: 2013-11-21
    Presentation of work at congresses

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    This paper introduces a novel on-chip measurement technique for the determination of the central frequency and 3dB bandwidth of a 60GHz power amplifier (PA) by performing low frequency temperature measurements in silicon integrated circuits. The techniques is implemented by using a temperature sensor embedded in the same silicon die as the PA, and placed in empty spaces next to it. Results confirm that temperature sensors can be used as functional built-in testers which serve to reduce testing costs and enhance yield as part of self-healing strategies.

  • Inductor shielding strategies to protect mmW LC-VCOs from high frequency substrate noise

     Molina García, Marc-Manel; Aragones Cervera, Xavier; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Microelectronics journal
    Date of publication: 2013-05-01
    Journal article

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    This paper analyzes the impact of high-frequency substrate noise on two 60 GHz LC-VCOs that implement different strategies for inductor shielding, namely floating and grounded shields. An analytical model, which has previously shown very good accuracy up to 7 GHz, is used to identify the circuit parameters that determine the level of the spurs created by the noise. These parameters are individually evaluated for the two VCOs, identifying their relative responsibility for the observed noise effects. The analysis concludes that a floating inductor shield provides extra immunity compared to a grounded inductor shield, and that this advantage is essentially due to the improvement in the tank quality factor. The predictions of the analytical model are validated by comparing them with circuit simulations and measurements of the noise impact on the two VCOs manufactured in a 65 nm CMOS technology, proving its usefulness at mm-wave frequencies.

    This paper analyzes the impact of high-frequency substrate noise on two 60 GHz LC-VCOs that implement different strategies for inductor shielding, namely floating and grounded shields. An analytical model, which has previously shown very good accuracy up to 7 GHz, is used to identify the circuit parameters that determine the level of the spurs created by the noise. These parameters are individually evaluated for the two VCOs, identifying their relative responsibility for the observed noise effects. The analysis concludes that a floating inductor shield provides extra immunity compared to a grounded inductor shield, and that this advantage is essentially due to the improvement in the tank quality factor. The predictions of the analytical model are validated by comparing them with circuit simulations and measurements of the noise impact on the two VCOs manufactured in a 65 nm CMOS technology, proving its usefulness at mm-wave frequencies.

  • Efficiency determination of RF linear power amplifiers by steady-state temperature monitoring using built-in sensors

     Altet Sanahujes, Josep; Gómez Salinas, Didac; Perpinyà, Xavier; Mateo Peña, Diego Cesar; González, José Luis; Vellvehi, Miquel; Jordà, Xavier
    Sensors and actuators A. Physical
    Date of publication: 2013-04
    Journal article

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    This work aims at showing a new approach for determining the efficiency of linear class A RF power amplifiers by means of non-invasive, steady-state thermal monitoring. The theoretical basis of the technique is indicated and its suitability in a real case application scenario is presented. More in detail, silicon surface thermal monitoring is performed with built-in sensors and infrared measurements on an RF power amplifier. The first monitoring circuit consists of differential sensors, which can be used for contact-less on-line efficiency monitoring or to easy production testing. The obtained results are corroborated by means of Infrared measurements. Off-chip temperature sensors have applications in failure analysis or circuit debugging scenarios. As a result, we observe a good agreement between the efficiency predicted with the thermal measurements (less than 5% of error) when compared to values measured with standard electrical equipment.

    This work aims at showing a new approach for determining the efficiency of linear class A RF power amplifiers by means of non-invasive, steady-state thermal monitoring. The theoretical basis of the technique is indicated and its suitability in a real case application scenario is presented. More in detail, silicon surface thermal monitoring is performed with built-in sensors and infrared measurements on an RF power amplifier. The first monitoring circuit consists of differential sensors, which can be used for contact-less on-line efficiency monitoring or to easy production testing. The obtained results are corroborated by means of Infrared measurements. Off-chip temperature sensors have applications in failure analysis or circuit debugging scenarios. As a result, we observe a good agreement between the efficiency predicted with the thermal measurements (less than 5% of error) when compared to values measured with standard electrical equipment.

  • Design of Reconfigurable RF circuits for Self-Compensation

     Gómez Salinas, Dídac
    Defense's date: 2013-01-25
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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  • On line monitoring of RF power amplifiers with embedded temperature sensors

     Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Gómez Salinas, Dídac
    IEEE International On-Line Testing Symposium
    Presentation's date: 2012-06-29
    Presentation of work at congresses

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  • Electro-thermal characterization of a differential temperature sensor and the thermal coupling in a 65nm CMOS IC

     Altet Sanahujes, Josep; Gonzalez Jimenez, Jose Luis; Gómez Salinas, Dídac; Perpiñà Gilabet, Xavier; Grauby, Stéphane; Dufis, Cédric; Vellvehi, Miquel; Mateo Peña, Diego Cesar; Dilhaire, Stephan; Jordà, Xavier
    International Workshop on Thermal Investigations of ICs and Systems
    Presentation's date: 2012-09-25
    Presentation of work at congresses

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    This paper explains the design decisions and the different measurements we have done in order to characterize the thermal coupling and the ch aracteristics of temperature sensors embedded in a integrated circuit implemented in a CMOS 65nm technology. The circu it contains a 2GHz linear power amplifier, MOS transistors behaving as heat sources and two differential temperatu re sensors. Temperature measurements performed with the embedded sensor are corroborated with an Infra-Red camera and a laser interferometer used as thermometer.

  • DC temperature measurements for power gain monitoring in RF power amplifiers

     Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Gómez Salinas, Didac; Perpiñà Gilabet, Xavier; Jordà, Xavier
    IEEE International Test Conference
    Presentation's date: 2012-11-05
    Presentation of work at congresses

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    In this paper we demonstrate that the steady state temperature increase due to the power dissipated by the circuit under test can be used as observable to test the gain of a 2GHz linear class A Power Amplifier. As a proof of concept, we use two strategies to monitor the temperature: a temperature sensor embedded within the same silicon die, which can be used for a BIST approach, and an Infra Red camera, with applications to failure analysis and product debugging.

    In this paper we demonstrate that the steady state temperature increase due to the power dissipated by the circuit under test can be used as observable to test the gain of a 2GHz linear class A Power Amplifier. As a proof of concept, we use two strategies to monitor the temperature: a temperature sensor embedded within the same silicon die, which can be used for a BIST approach, and an Infra Red camera, with applications to failure analysis and product debugging.

  • A high dynamic-range RF programmable-gain front end for G.hn RF-Coax in 65-nm CMOS

     Trulls Fortuny, Xavier; Mateo Peña, Diego Cesar; Bofill, Adrià
    IEEE transactions on microwave theory and techniques
    Date of publication: 2012-10
    Journal article

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    A high-dynamic-range programmable-gain inductorless RF front end suitable for the RF-coax bandplan of the G.hn recommendation is presented. A double-input RF programmable gain amplifier (DI-RFPGA) with switchable capacitive attenuation providing four gain settings is used at the input, followed by a current reuse transconductance amplifier (CR-TCA) and a switching stage for frequency downconversion. Besides the gain configurability provided by the DI-RFPGA, the front end adds an additional configuration mechanism by allowing the bypass of the CR-TCA, connecting the DI-RFPGA directly to the switching stage, and thereby providing a total of eight gain settings. The different sets of specifications result in a signal-to-noise-plus-distortion ratio larger than 37 dB for an input power range from 78 to 5 dBm with a bandwidth from 300 MHz to 2.5 GHz. The chip is fabricated in a 65-nm CMOS technology and consumes between 31.8–46.8 mW. The RF front end achieves a voltage gain range of 39.2 dB, with a maximum voltage gain of 25.2 dB, a minimum noise figure of 5.5 dB, and a maximum third-order intermodulation intercept point of 24.2 dBm. The circuit occupies a total area of 0.119 mm.

  • On the use of static temperature measurements as process variation observable

     Gómez Salinas, Didac; Altet Sanahujes, Josep; Mateo Peña, Diego Cesar
    Journal of electronic testing. Theory and applications
    Date of publication: 2012-10
    Journal article

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    In this paper we present the use of static temperature measurements as process variation observable. Contrary to previously published thermal testing methods, the proposed methodology does not need an excitation signal, thus reducing test cost and improving built-in capabilities of thermal monitoring. The feasibility of the technique and a complete test methodology is presented using a narrowband LNA as example. Finally, a complete electro-thermal co-simulation test bench between the LNA and a differential temperature sensor embedded in the same silicon die is presented in order to validate the results. Results prove that RF figures of merit can be extracted from DC temperature measurements done without loading or exciting the RF circuit under test.

  • A small-area inductorless configurable wideband LNA with high dynamic range

     Trulls Fortuny, Xavier; Mateo Peña, Diego Cesar; Bofill, Adrià
    Microelectronics journal
    Date of publication: 2012-03
    Journal article

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  • Design of broadband inductor-less RF front-ends with high dynamic range for G.hn

     Trulls Fortuny, Xavier
    Defense's date: 2012-07-06
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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  • Design of Frequency Divider with Voltage Controlled Oscillator for 60 GHz Low Power Phase-Locked Loops in 65 nm RF CMOS  Open access

     Brandano, Davide
    Defense's date: 2012-03-09
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 GHz is in today's technology a great challenge. A key reason is the inaccuracy of CMOS active and passive device models at mm-W. Three critical issues still constitute research objectives at 60 GHz in CMOS: generation of the Local Oscillator (LO) signal (1), division of the LO signal for the Phase-Locked Loop (PLL) closed loop (2) and distribution of the LO signal (3). In this Thesis, all those three critical issues are addressed and experimentally faced-up: a divide-by-2 FD for a PLL of a direct-conversion transceiver operating at mm-W frequencies in 65 nm RF CMOS technology has been designed. Critical issues such as Process, Voltage and Temperature (PVT) variations, Electromagnetic (EM) simulations and power consumption are addressed to select and design a FD with high frequency dividing range. A 60 GHz VCO is co-designed and integrated in the same die, in order to provide the FD with mm-W input signal. VCOs and FDs play critical roles in the PLL. Both of them constitute the PLL core components and they would need co-design, having a big impact in the overall performance especially because they work at the highest frequency in the PLL. Injection Locking FD (ILFD) has been chosen as the optimum FD topology to be inserted in the control loop of mm-W PLL for direct-conversion transceiver, due to the high speed requirements and the power consumption constraint. The drawback of such topology is the limited bandwidth, resulting in narrow Locking Range (LR) for WirelessHDTM applications considering the impact of PVT variations. A simulation methodology is presented in order to analyze the ILFD locking state, proposing a first divide-by-2 ILFD design with continuous tuning. In order to design a wide LR, low power consumption ILFD, the impacts of various alternatives of low/high Q tank and injection scheme are deeply analysed, since the ILFD locking range depends on the Q of the tank and injection efficiency. The proposed 3-bit dual-mixing 60 GHz divide-by-2 LC-ILFD is designed with an accumulation of switching varactors binary scaled to compensate PVT variations. It is integrated in the same die with a 4-bit 60 GHz LC-VCO. The overall circuit is designed to allow measurements of the singles blocks stand-alone and working together. The co-layout is carried on with the EM modelling process of passives devices, parasitics and transmission lines extracted from the layout. The inductors models provided by the foundry are qualified up to 40 GHz, therefore the EM analysis is a must for post-layout simulation. The PVT variations have been simulated before manufacturing and, based on the results achieved, a PLL scheme PVT robust, considering frequency calibration, has been patented. The test chip has been measured in the CEA-Leti (Grenoble) during a stay of one week. The operation principle and the optimization trade-offs among power consumption, and locking ranges of the final selected ILFD topology have been demonstrated. Even if the experimental results are not completely in agreement with the simulations, due to modelling error and inaccuracy, the proposed technique has been validated with post-measurement simulations. As demonstrated, the locking range of a low-power, discrete tuned divide-by-2 ILFD can be enhanced by increasing the injection efficiency, without the drawbacks of higher power consumption and chip area. A 4-bits wide tuning range LC-VCO for mm-W applications has been co-designed using the selected 65 nm CMOS process.

  • Electro-thermal coupling analysis methodology for RF circuits

     Gómez Salinas, Didac; Dufis, Cédric; Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Microelectronics journal
    Date of publication: 2012-09
    Journal article

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  • Sensor de temperatura diferencial con inmunidad a interferencias térmicas

     Altet Sanahujes, Josep; Gómez Salinas, Dídac; Mateo Peña, Diego Cesar
    Date of request: 2012-11-22
    Invention patent

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  • Circuito electrònico con magnitud eléctrica de salida dependiente de la diferencia de tensión de dos nodos de entrada y de la diferencia de temperatura de dos de sus dispositivos

     Mateo Peña, Diego Cesar; Altet Sanahujes, Josep; Gómez Salinas, Dídac
    Date of request: 2012-02-23
    Invention patent

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    Circuito electrónico con magnitud eléctrica de salida dependiente de la diferencia de tensión de dos nodos de entrada y de la diferencia de temperatura de dos de sus dispositivos.

    La presente invención describe un circuito electrónico cuya magnitud eléctrica de salida depende de la diferencia de tensión de dos de los nodos de entrada del mismo así como de la diferencia de temperatura de dos de sus dispositivos internos. La figura 1 muestra el símbolo del circuito electrónico. Éste tiene como entradas eléctricas dos entradas en tensión (2) y (3) y dos entradas de alimentación (6) y (7), y como salida tiene un nodo (1). Además, tiene dos dispositivos internos (4) y (5) cuya diferencia de temperaturas influirá de forma directa en el valor de la magnitud eléctrica del nodo de salida. En el circuito de la presente invención la variación de la magnitud eléctrica de la salida (1) depende de la diferencia de tensión de los dos nodos de entrada (2) y (3) así como de la diferencia de temperaturas de los dispositivos internos (4) y (5).

  • Procedimiento para la medición de la eficiencia de amplificadores de potencia integrados lineales clase A utilizando mediciones de temperatura en continua

     Mateo Peña, Diego Cesar; Altet Sanahujes, Josep; Gómez Salinas, Dídac
    Date of request: 2012-02-15
    Invention patent

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    Procedimiento para la medición de la eficiencia de amplificadores de potencia integrados lineales clase A utilizando mediciones de temperatura en continua.

    La presente invención describe un procedimiento para la medición de la eficiencia de amplificadores de potencia integrados lineales clase A utilizando mediciones de temperatura en continua. La Fig. 1 muestra un circuito integrado (1) que contiene un amplificador lineal de potencia clase A (2). La figura también muestra el generador que suministra una tensión continua para alimentar al amplificador (3) y el generador de señal (4) que el amplificador amplifica y entrega a la carga (5). Mediciones de la componente continua de la temperatura en puntos seleccionados del circuito integrado, en este caso el punto (6), permiten la medición de la eficiencia del amplificador sin necesidad de utilizar equipos de medición de señales analógicas alta frecuencia.

  • Non-invasive Monitoring of CMOS Power Amplifiers Operating at RF and mmW Frequencies using an On-chip Thermal Sensor

     Gonzalez Jimenez, Jose Luis; Martineau, Baudouin; Mateo Peña, Diego Cesar; Altet Sanahujes, Josep
    IEEE Radio Frequency Integrated Circuits Symposium
    Presentation's date: 2011-06-06
    Presentation of work at congresses

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    In this paper a non-invasive, contact-less technique for the on-chip observation of PA operation is presented. It uses a differential temperature sensor that transduces the temperature increase due to the power dissipated by active transistors operating at high frequencies into a low frequency signal that is proportional to some relevant PA figures of merit, such as output power or PAE. The technique is demonstrated by using the same thermal sensor in two different PAs (a 2 GHz PA and a 60 GHz PA) implemented with a 65 nm CMOS process.

  • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

     Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Gonzalez Jimenez, Jose Luis; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Gonzalez Colas, Antonio Maria
    IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era
    Presentation's date: 2011-04-06
    Presentation of work at congresses

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    Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90 nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.

  • A 16-kV HBM RF ESD Protection Codesign for a 1-mW CMOS Direct Conversion Receiver Operating in the 2.4-GHz ISM Band

     Gonzalez Jimenez, Jose Luis; Solar, H.; Adin, Iñigo; Mateo Peña, Diego Cesar; Berenguer, Roc
    IEEE transactions on microwave theory and techniques
    Date of publication: 2011-09
    Journal article

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  • Design of a 2.5-GHZ QVCO robust against high frequency substrate noise

     Molina Garcia, Marc Manel; Gómez Salinas, Dídac; Aragones Cervera, Xavier; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Microwave and optical technology letters
    Date of publication: 2011-07
    Journal article

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    This work presents the design procedure followed to obtain a low-power voltage-controlled oscillator (VCO) robust against high-frequency substrate noise, using as a demonstrator a 2.5 GHz VCO with quadrature outputs (QVCO) based on a 5-GHz LC tank resonant VCO (LC-VCO) and frequency divider. A simple, intuitive, and easy to handle analytical model is proposed to identify the design parameters that contribute to the performance degradation of LC-VCOs due to the effect of high frequency substrate noise. The guidelines obtained have been applied in the design of the low-power QVCO. Finally, the work discusses several trade-offs that can be used to maximize the immunity of a LC-VCO against substrate noise.

  • Prediction of the impact of substrate coupled switching noise on Frequency Synthesizers, using high-level analysis and models

     Osorio Tamayo, Juan Felipe
    Defense's date: 2011-07-11
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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  • A low-power impulse radio ultra-wideband transceiver for short-range, high-speed wireless communications

     Barajas Ojeda, Enrique
    Defense's date: 2011-08-29
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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  • Nonlinearity characterization of temperature sensing systems for integrated circuit testing by intermodulation products monitoring

     Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Perpiñà Gilabet, Xavier; Grauby, Stéphane; Dilhaire, Stefan; Jordà, Xavier
    Review of scientific instruments
    Date of publication: 2011-09
    Journal article

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  • Electrothermal design procedure to observe RF circuit power and linearity characteristics with a homodyne differential temperature sensor

     Onabajo, M.; Altet Sanahujes, Josep; Aldrete Vidrio, Hector Eduardo; Mateo Peña, Diego Cesar; Silva Martinez, Jose
    IEEE transactions on circuits and systems I: regular papers
    Date of publication: 2011-03
    Journal article

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  • Survey of robustness enhancement techniques for wireless systems-on-a-chip and study of temperature as observable for process variations

     Onabajo, M.; Gómez Salinas, Dídac; Aldrete Vidrio, Hector Eduardo; Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Silva Martinez, Jose
    Journal of electronic testing. Theory and applications
    Date of publication: 2011-06
    Journal article

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    Built-in test and on-chip calibration features are becoming essential for reliable wireless connectivity of next generation devices suffering from increasing process variations in CMOS technologies. This paper contains an overview of contemporary self-test and performance enhancement strategies for single-chip transceivers. In general, a trend has emerged to combine several techniques involving process variability monitoring, digital calibration, and tuning of analog circuits. Special attention is directed towards the investigation of temperature as an observable for process variations, given that thermal coupling through the silicon substrate has recently been demonstrated as mechanism to monitor the performances of analog circuits. Both Monte Carlo simulations and experimental results are presented in this paper to show that circuit-level specifications exhibit correlations with silicon surface temperature changes. Since temperature changes can be measured with efficient on-chip differential temperature sensors, a conceptual outline is given for the use of temperature sensors as alternative process variation monitors.

  • Procedimiento para la estimación de caracteristicas eléctricas de un circuito analógico mediante la medición en continua de temperatura

     Gómez Salinas, Dídac; Mateo Peña, Diego Cesar; Altet Sanahujes, Josep
    Date of request: 2011-12-23
    Invention patent

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    Procedimiento para la estimación de características eléctricas de un circuito analógico mediante la medición en continua de temperatura.

    La presente invención describe un procedimiento para la estimación de características eléctricas de circuitos analógicos integrados en un cristal semiconductor mediante la medición en continua de la temperatura. La fig. 1 muestra un cristal semiconductor (1) que puede contener diferentes circuitos analógicos (2). Por ejemplo, y sin que la lista limite los ámbitos de aplicación del presente procedimiento, la figura muestra un amplificador. Este amplificador dispone de entradas de señal (4) y entradas de la tensión de alimentación (3). La polarización del circuito en continua aplicando una tensión a las entradas de alimentación (3), sin aplicar señal a las entradas (4), provoca que los dispositivos que forman el amplificador disipen potencia. Mediciones del incremento de temperatura provocada por esta disipación de potencia en puntos seleccionados del semiconductor (5) permiten obtener características del circuito analógico, tales como, y sin que la lista limite los ámbitos de aplicación del presente procedimiento, ganancia de amplificadores. La medida de la temperatura se realiza en continua y puede hacerse bien mediante sensores de temperatura integrados en el mismo cristal semiconductor, bien mediante sensores externos.

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    Behavioural modelling of DLLs for fast simulation and optimisation of jitter and power consumption  Open access

     Barajas Ojeda, Enrique; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Euromicro Symposium on Digital Systems Design
    Presentation's date: 2010-09-02
    Presentation of work at congresses

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    This paper presents a behavioural model for fast DLL simulations. The behavioural model includes a modelling of the various noise sources in the DLL that produce output jitter. The model is used to obtain the dependence of the output jitter versus the power consumption. The model exploits the open-loop DLL analysis to reduce simulation time when compared to typical DLL evaluation.

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    Electro-thermal coupling analysis methodology for RF circuits  Open access

     Gómez Salinas, Didac; Mateo Peña, Diego Cesar; Altet Sanahujes, Josep
    International Workshop on Thermal Investigations of ICs and Systems
    Presentation of work at congresses

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    In this paper we present an electro-thermal coupling simulation technique for RF circuits. The proposed methodology takes advantage of well established tools for frequency translating circuits in order to significantly reduce the computational resources needed when frequencies of interest are separated by orders of magnitude.

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    Design of reconfigurable RF circuits for self compensation  Open access

     Gómez Salinas, Dídac; Mateo Peña, Diego Cesar
    Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing
    Presentation's date: 2010-10-21
    Presentation of work at congresses

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    In this paper we will show how a combination of design choices allows for the design of a PVT robust RF front-end with minimum area, power and nominal specifications penalty.

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    On evaluating temperature as observable for CMOS technology variability  Open access

     Altet Sanahujes, Josep; Gómez Salinas, Dídac; Dufis, Cédric Yvan; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    European workshop on CMOS Variability
    Presentation's date: 2010-05-26
    Presentation of work at congresses

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    The temperature at surface of a silicon die depends on the activity of the circuits placed on it. In this paper, it is analyzed how Process, Voltage and Temperature (PVT) variations affect simultaneously some figures of merit (FoM) of some digital and analog circuits and the power dissipated by such circuits. It is shown that in some cases, a strong correlation exists between the variation of the circuit FoM and the variation of the dissipated power. Since local temperature increase at the silicon surface close to the circuit linearly depends on dissipated power, the results show that temperature can be considered as an observable magnitude for CMOS technology variability monitoring.

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    DLL's behavioral modeling for power consumption and jitter fast optimization  Open access

     Barajas Ojeda, Enrique; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2010-11-18
    Presentation of work at congresses

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    This paper analyzes the sources of jitter in a DLL and presents a behavioral model for fast DLL optimization. An algorithm to simulate the DLL in open loop is demonstrated. This procedure, together with the behavioral modeling, greatly reduces the simulation time of DLL when compared to the closeloop DLL simulation. In order to optimize the DLL performance, the dependence of the output jitter versus the power consumption is studied.

    Postprint (author’s final draft)

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    A 75 pJ/bit all-digital quadrature coherent IR-UWB transceiver in 0.18 um CMOS  Open access

     Barajas Ojeda, Enrique; Gómez Salinas, Dídac; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    IEEE Radio Frequency Integrated Circuits Symposium
    Presentation's date: 2010-05-24
    Presentation of work at congresses

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    In this paper a 75 pJ/b all-digital quadrature coherent impulse radio ultra-wideband transceiver in 0.18 μm CMOS is presented. It consumes 42 mW operating at a 560 Mbps datarate. The receiver and transmitter share most of the components reducing the area. This design is optimal for low-power low-cost short-range high-speed communications.

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    Providing an UWB-IR BAN wireless communications network and its application to design a low power transceiver in CMOS technology  Open access

     Barajas Ojeda, Enrique; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing
    Presentation's date: 2010-10-21
    Presentation of work at congresses

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    Ultra Wide-Band (UWB) communication techniques have received increasing attention since United States Federal Communications Commission (FCC) adopted a “First Report and Order” in 2002. Unfortunately the regulations that appeared a few years latter didn't have the same level of commitment and had much tighter constraints. The FCC part. 15 power spectral density limitation is depicted. Although the word-wide common bandwidth is quite scarce (7.25 to 8.5 GHz), UWB still has its niche applications. Impulse Radio (IR) implementation of UWB systems has very interesting features such as low complexity, low power consumption, low cost, high data-rate, and the ability of coexistence with other radio systems.

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    Effect of high frequency substrate noise on LC-VCOs  Open access

     Molina Garcia, Marc Manel; Aragones Cervera, Xavier; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2010-08-03
    Presentation of work at congresses

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    This paper presents an experimental analysis of the performance degradation of an LC-Voltage Controlled Oscillator (LC-VCO) produced by high frequency noise present in the substrate. The spurs observed are shown to be caused by a frequency pulling mechanism. Based on the theory of injection locked oscillators, a new analytical model to predict the behavior of the LC-VCO under the effect of high frequency substrate noise is presented. The analytical model, which is successfully compared with experimental measurements on a 7 GHz LCVCO, provides rapid intuition on the relation between spurs and circuit parameters.

  • Exploiting CMOS short-channel effects for yield enhancement in analogue/RF design

     Gómez Salinas, Dídac; Mateo Peña, Diego Cesar
    Electronics Letters
    Date of publication: 2010-04-15
    Journal article

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  • STRATEGIES FOR BUILT-IN CHARACTERIZATION TESTING AND PERFORMANCE MONITORING OF ANALOG RF CIRCUITS WITH TEMPERATURE MEASUREMENTS

     Aldrete Vidrio, Hector Eduardo
    Defense's date: 2010-09-27
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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  • Congresos Temperatura en Circuitos Integrados y Amplificadores de Potencia

     Rubio Sola, Jose Antonio; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Altet Sanahujes, Josep
    Participation in a competitive project

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  • POWER AMPLIFIERS AND ANTENNAS FOR MOBILE APPLICATIONS.APLICACIÓN AL HOME NETWORKING, Projecte Europeu CATRENE

     Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Dufis, Cédric Yvan; Gonzalez Jimenez, Jose Luis
    Participation in a competitive project

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    Strategies for built-in characterization testing and performance monitoring of analog RF circuits with temperature measurements  Open access

     Aldrete Vidrio, Hector Eduardo; Mateo Peña, Diego Cesar; Altet Sanahujes, Josep; Amine Salhi, M.; Grauby, Stéphane; Dilhaire, Stefan; Onabajo, M.; Silva Martinez, Jose
    Measurement science and technology
    Date of publication: 2010-06-08
    Journal article

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    This paper presents two approaches to characterize RF circuits with built-in differential temperature measurements, namely the homodyne and heterodyne methods. Both non-invasive methods are analyzed theoretically and discussed with regard to the respective trade-offs associated with practical off-chip methodologies as well as on-chip measurement scenarios. Strategies are defined to extract the center frequency and 1 dB compression point of a narrow-band LNA operating around 1 GHz. The proposed techniques are experimentally demonstrated using a compact and efficient on-chip temperature sensor for built-in test purposes that has a power consumption of 15 μW and a layout area of 0.005 mm2 in a 0.25 μm CMOS technology. Validating results from off-chip interferometer-based temperature measurements and conventional electrical characterization results are compared with the on-chip measurements, showing the capability of the techniques to estimate the center frequency and 1 dB compression point of the LNA with errors of approximately 6% and 0.5 dB, respectively.

  • Heterodyne lock-in thermal coupling measurements in integrated circuits: Applications to test and characterization

     Altet Sanahujes, Josep; Aldrete Vidrio, Hector Eduardo; Aldrete-Vidrio, E; Mateo Peña, Diego Cesar; Salhi, A; Grauby, S; Claeys, W
    Review of scientific instruments
    Date of publication: 2009-02
    Journal article

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  • Modeling and design of reliable, process-variation aware nanoelectronic devices,circuits and systems

     Aragones Cervera, Xavier; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Perez Puigdemont, Jordi; Mauricio Ferré, Juan; Gómez Salinas, Dídac; Pons Solé, Marc; García Leyva, Lancelot; Gonzalez Jimenez, Jose Luis; Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja
    Participation in a competitive project

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  • POWER AMPLIFIERS AND ANTENNAS FOR MOBILE APPLICATIONS.APLICACIÓN AL HOME NETWORKING, Projecte Europeu CATRENE

     Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Dufis, Cédric Yvan; Gonzalez Jimenez, Jose Luis
    Participation in a competitive project

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  • CIMHOGAR 2: CONECTIVIDAD INTEGRAL MULTIMEDIA EN EL HOGAR

     Trulls Fortuny, Xavier; Mateo Peña, Diego Cesar; Molina Garcia, Marc Manel; Gonzalez Jimenez, Jose Luis
    Participation in a competitive project

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  • GRUP DE RECERCA DE CIRCUITS I SISTEMES INTEGRATS D'ALTES PRESTACIONS (HIPICS)

     Rubio Sola, Jose Antonio; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Gonzalez Jimenez, Jose Luis; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Molina Garcia, Marc Manel; Barajas Ojeda, Enrique; Gómez Salinas, Dídac; García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Pons Solé, Marc; Trulls Fortuny, Xavier; Dufis, Cédric Yvan; Landauer, Gerhard Martin; Garcia Almudever, Carmen; Perez Puigdemont, Jordi; Aymerich Capdevila, Nivard; Gomez Fernandez, Sergio; Aragones Cervera, Xavier
    Participation in a competitive project

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  • Modeling and design of reliable, process-variation aware nanoelectronic devices,circuits and systems

     Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Perez Puigdemont, Jordi; Mauricio Ferré, Juan; Gómez Salinas, Dídac; Pons Solé, Marc; García Leyva, Lancelot; Gonzalez Jimenez, Jose Luis; Moll Echeto, Francesc de Borja
    Participation in a competitive project

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  • SYNTHESIS USING ADVANCED PROCESS TECHNOLOGY INTEGRATED IN REGULAR CELLS, IPS, ARCHITECTURES,

     Gomez Fernandez, Sergio; Rubio Sola, Jose Antonio; Pons Solé, Marc; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Perez Puigdemont, Jordi; Moll Echeto, Francesc de Borja
    Participation in a competitive project

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    Non-invasive RF built-in testing using on-chip temperature sensors  Open access

     Aldrete Vidrio, Hector Eduardo; Onabajo, M.; Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Silva-Martínez, José
    IEEE International Test Conference
    Presentation's date: 2009-11
    Presentation of work at congresses

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    This poster shows how to efficiently observe high-frequency figures of merit in RF circuits by measuring DC temperature with CMOS-compatible built-in sensors.

  • A heterodyne method for the thermal observation of the electrical behavior of high-frequency integrated circuits

     Altet Sanahujes, Josep; Aldrete-Vidrio, E; Aldrete Vidrio, Hector Eduardo; Mateo Peña, Diego Cesar; Perpiñà Gilabet, Xavier; Jordà, X; Vellvehi, M; Millán, J; Salhi, A; Grauby, S; Claeys, W; Dilhaire, S
    Measurement science and technology
    Date of publication: 2008-09
    Journal article

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  • Using temperature as observable of the frequency response of RF CMOS amplifiers

     Aldrete Vidrio, Hector Eduardo; Slhi, M A; Altet Sanahujes, Josep; Gruby, S; Mateo Peña, Diego Cesar; Michel, H; Clerjaud, L; Rampnous, J M; Rubio Sola, Jose Antonio; Dilhaire, W Claeys I S; Aldrete-Vidrio, E
    13th European Test Symposium
    Presentation of work at congresses

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  • A Low-Power RF Front-End for 2.5 GHz Receivers

     Moreno, L; Gómez, D; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Berenguer, R; Solar, H
    IEEE International Symposium on Circuits and Systems
    Presentation of work at congresses

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