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  • Opportunities for Radio Frequency Nanoelectronic Integrated Circuits Using Carbon-Based Technologies  Open access

     Landauer, Gerhard Martin
    Defense's date: 2014-07-07
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    Aquesta tesi mostra el treball realitzat en modelització i prediccions de prestacions de transistors de nanotubs de carboni (CNFET) i transistors de grafè (GFET). Mentre es preveu que el CMOS convencional basat en silici arribi als límits d¿escalat durant la pròxima dècada, aquestes noves tecnologies són dues prometedores candidates per una futura electrònica d'alta prestació. L¿objectiu principal d'aquesta tesi és investigar les oportunitats que genera l¿ús d¿aquestes tecnologies basades en carboni per circuits integrats RF. Aquesta tesi profunditza en 1) la modelització del soroll i de la variabilitat de procés de CNFETs, 2) prediccions de prestacions RF per CNFETs, i 3) un model compacte exacte del GFET.Aquest treball proposa el primer model de soroll compacte de CNFET existent. El soroll és d¿una gran importància per les aplicacions RF i el fet de tenir-lo en compte enriqueix significativament els resultats obtinguts mitjançant simulacions. Es presenta, a més, un model de variabilitat del CNFET que considera les imperfeccions de síntesi de tubs i d¿eliminació de tubs metàl¿lics. Aquestes dues extensions de model han sigut afegides al model compacte de CNFET de Stanford i permeten l¿avaluació, tenint en compte la variabilitat, de les prestacions RF d¿aquesta tecnologia CNFET.La predicció de les prestacions dels CNFETs es presenta tant a nivell de dispositiu com a nivell de circuit. Es presenta el conjunt de figures de mèrit de requisits tecnològics RF-CMOS de l¿International Technology Roadmap for Semiconductors (ITRS) que demostren que els CNFETs tenen prestacions excel¿lents en termes de velocitat, guany i la figura de soroll mínima. També es demostra que la disminució de mida del CNFET aporta una millora significativa de les seves prestacions. Aquestes anàlisis confirmen que el CNFET té un gran potencial per superar el Si-CMOS convencional en aplicacions de RF.Una tercera contribució clau d¿aquesta tesi és el desenvolupament d¿un model compacte precís per GFETs. Existeixen models compactes anteriors que simplifiquen certs aspectes físics tot causant resultats de simulació erronis. S¿ha proposat, implementat en Verilog-A, un model senzill però precís de la relació corrent-tensió del GFET. L¿anàlisi de l¿error tant del model proposat com dels models actualment existents subratlla els avantatges del nou mètode. A més, el model s¿ha verificat respecte resultats experimentals. El model del GFET desenvolupat és un pas important cap a una millor comprensió de les característiques i les oportunitats de circuits analògics basats en grafè.

    This thesis presents a body of work on the modeling of and performance predictions for carbon nanotube field-effect transistors (CNFET) and graphene field-effect transistors (GFET). While conventional silicon-based CMOS is expected to reach its ultimate scaling limits during the next decade, these two novel technologies are promising candidates for future high-performance electronics. The main goal of this work is to investigate on the opportunities of using such carbon-based electronics for RF integrated circuits. This thesis addresses 1) the modeling of noise and process variability in CNFETs, 2) RF performance predictions for CNFETs, and 3) an accurate GFET compact model. This work proposes the first CNFET noise compact model. Noise is of primary importance for RF applications and its description significantly increases the insight gained from simulation studies. Furthermore, a CNFET variability model is presented, which handles tube synthesis and metal tube removal imperfections. These two model extensions have been added to the Stanford CNFET compact model and allow for the variability-aware RF performance assessment of the CNFET technology. In continuation, comprehensive RF performance projections for CNFETs are provided both on the device and circuit level. The overall set of ITRS RF-CMOS technology requirement FoMs is determined and shows that the CNFET performs excellently in terms of speed, gain, and minimum noise figure. Furthermore, for the first time FoMs are reported for the basic RF building blocks low-noise amplifier and oscillator. In addition, it is shown that CNFET downscaling yields significant performance improvements. Based on these analyses it is confirmed that the CNFET has the potential to outperform Si-CMOS in RF applications. A third key contribution of this thesis is the development of an accurate GFET compact model. Previous compact models simplify several physical aspects, which can cause erroneous simulation results. Here, an accurate yet simple mathematical description of the GFET’s current-voltage relation is proposed and implemented in Verilog-A. Comprehensive error analyses are done in order to highlight the advantages of the new approach. Furthermore, the model is verified against measurement results. The developed GFET model is an important step towards better understanding the characteristics and opportunities of graphene-based analog circuitry.

  • Inductor shielding strategies to protect mmW LC-VCOs from high frequency substrate noise

     Molina García, Marc-Manel; Aragones Cervera, Xavier; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Microelectronics journal
    Date of publication: 2013-05-01
    Journal article

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    This paper analyzes the impact of high-frequency substrate noise on two 60 GHz LC-VCOs that implement different strategies for inductor shielding, namely floating and grounded shields. An analytical model, which has previously shown very good accuracy up to 7 GHz, is used to identify the circuit parameters that determine the level of the spurs created by the noise. These parameters are individually evaluated for the two VCOs, identifying their relative responsibility for the observed noise effects. The analysis concludes that a floating inductor shield provides extra immunity compared to a grounded inductor shield, and that this advantage is essentially due to the improvement in the tank quality factor. The predictions of the analytical model are validated by comparing them with circuit simulations and measurements of the noise impact on the two VCOs manufactured in a 65 nm CMOS technology, proving its usefulness at mm-wave frequencies.

    This paper analyzes the impact of high-frequency substrate noise on two 60 GHz LC-VCOs that implement different strategies for inductor shielding, namely floating and grounded shields. An analytical model, which has previously shown very good accuracy up to 7 GHz, is used to identify the circuit parameters that determine the level of the spurs created by the noise. These parameters are individually evaluated for the two VCOs, identifying their relative responsibility for the observed noise effects. The analysis concludes that a floating inductor shield provides extra immunity compared to a grounded inductor shield, and that this advantage is essentially due to the improvement in the tank quality factor. The predictions of the analytical model are validated by comparing them with circuit simulations and measurements of the noise impact on the two VCOs manufactured in a 65 nm CMOS technology, proving its usefulness at mm-wave frequencies.

  • Electro-thermal coupling analysis methodology for RF circuits

     Gómez Salinas, Didac; Dufis, Cédric; Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Microelectronics journal
    Date of publication: 2012-09
    Journal article

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  • On the electrical properties of slotted metallic planes in CMOS processes for RF and millimeter-wave applications

     Gonzalez Jimenez, Jose Luis; Martineau, Baudouin; Belot, Didier
    Microelectronics journal
    Date of publication: 2012-05-17
    Journal article

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  • Design of Frequency Divider with Voltage Controlled Oscillator for 60 GHz Low Power Phase-Locked Loops in 65 nm RF CMOS  Open access

     Brandano, Davide
    Defense's date: 2012-03-09
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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    Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 GHz is in today's technology a great challenge. A key reason is the inaccuracy of CMOS active and passive device models at mm-W. Three critical issues still constitute research objectives at 60 GHz in CMOS: generation of the Local Oscillator (LO) signal (1), division of the LO signal for the Phase-Locked Loop (PLL) closed loop (2) and distribution of the LO signal (3). In this Thesis, all those three critical issues are addressed and experimentally faced-up: a divide-by-2 FD for a PLL of a direct-conversion transceiver operating at mm-W frequencies in 65 nm RF CMOS technology has been designed. Critical issues such as Process, Voltage and Temperature (PVT) variations, Electromagnetic (EM) simulations and power consumption are addressed to select and design a FD with high frequency dividing range. A 60 GHz VCO is co-designed and integrated in the same die, in order to provide the FD with mm-W input signal. VCOs and FDs play critical roles in the PLL. Both of them constitute the PLL core components and they would need co-design, having a big impact in the overall performance especially because they work at the highest frequency in the PLL. Injection Locking FD (ILFD) has been chosen as the optimum FD topology to be inserted in the control loop of mm-W PLL for direct-conversion transceiver, due to the high speed requirements and the power consumption constraint. The drawback of such topology is the limited bandwidth, resulting in narrow Locking Range (LR) for WirelessHDTM applications considering the impact of PVT variations. A simulation methodology is presented in order to analyze the ILFD locking state, proposing a first divide-by-2 ILFD design with continuous tuning. In order to design a wide LR, low power consumption ILFD, the impacts of various alternatives of low/high Q tank and injection scheme are deeply analysed, since the ILFD locking range depends on the Q of the tank and injection efficiency. The proposed 3-bit dual-mixing 60 GHz divide-by-2 LC-ILFD is designed with an accumulation of switching varactors binary scaled to compensate PVT variations. It is integrated in the same die with a 4-bit 60 GHz LC-VCO. The overall circuit is designed to allow measurements of the singles blocks stand-alone and working together. The co-layout is carried on with the EM modelling process of passives devices, parasitics and transmission lines extracted from the layout. The inductors models provided by the foundry are qualified up to 40 GHz, therefore the EM analysis is a must for post-layout simulation. The PVT variations have been simulated before manufacturing and, based on the results achieved, a PLL scheme PVT robust, considering frequency calibration, has been patented. The test chip has been measured in the CEA-Leti (Grenoble) during a stay of one week. The operation principle and the optimization trade-offs among power consumption, and locking ranges of the final selected ILFD topology have been demonstrated. Even if the experimental results are not completely in agreement with the simulations, due to modelling error and inaccuracy, the proposed technique has been validated with post-measurement simulations. As demonstrated, the locking range of a low-power, discrete tuned divide-by-2 ILFD can be enhanced by increasing the injection efficiency, without the drawbacks of higher power consumption and chip area. A 4-bits wide tuning range LC-VCO for mm-W applications has been co-designed using the selected 65 nm CMOS process.

  • Design of a fully integrated CMOS self-testable RF power amplifier using a thermal sensor

     Deltimple, Nathalie; Gonzalez Jimenez, Jose Luis; Altet Sanahujes, Josep; Luque, Yohann; Kerhervé, Eric
    European Solid-State Circuits Conference
    Presentation's date: 2012-09-21
    Presentation of work at congresses

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  • A compact noise model for carbon nanotube FETs

     Landauer, Gerhard Martin; Gonzalez Jimenez, Jose Luis
    International Semiconductor Conference Dresden-Grenoble
    Presentation's date: 2012-09-24
    Presentation of work at congresses

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    This paper focuses on the development of a compact noise model for radiofrequency (RF) carbon nanotube field-effect transistors (CNFET). The noise mechanisms in these devices are discussed and the impact of the different noise sources is analyzed. For the RF-CNFET under investigation a mínimum noise figure NFmin = 0.104 dB at 60 GHz is predicted. Our model is usable with conventional circuit simulators, which provides a basis for further investigations on CNFET-based RF Building blocks.

    This paper focuses on the development of a compact noise model for radiofrequency (RF) carbon nanotube field-effect transistors (CNFET). The noise mechanisms in these devices are discussed and the impact of the different noise sources is analyzed. For the RF-CNFET under investigation a mínimum noise figure NFmin = 0.104 dB at 60 GHz is predicted. Our model is usable with conventional circuit simulators, which provides a basis for further investigations on CNFET-based RF Building blocks.

  • Carbon nanotube FET process variability and noise model for radiofrequency investigations

     Landauer, Gerhard Martin; Gonzalez Jimenez, Jose Luis
    IEEE International Conference on Nanotechnology
    Presentation's date: 2012
    Presentation of work at congresses

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    This work focuses on process variability and noise in carbon nanotube field-effect transistors (CNFET) to obtain a compact model usable for radiofrequency (RF) design and simulations. CNFET figures of merit (FoM) are determined and compared to International Technology Roadmap for Semiconductors (ITRS) requirements on conventional analog silicon-based devices. The developed model is also used to investigate on the impact of manufacturing process variability on the CNFET's RF-performance and noise behavior.

  • Electro-thermal characterization of a differential temperature sensor and the thermal coupling in a 65nm CMOS IC

     Altet Sanahujes, Josep; Gonzalez Jimenez, Jose Luis; Gómez Salinas, Dídac; Perpiñà Gilabet, Xavier; Grauby, Stéphane; Dufis, Cédric; Vellvehi, Miquel; Mateo Peña, Diego Cesar; Dilhaire, Stephan; Jordà, Xavier
    International Workshop on Thermal Investigations of ICs and Systems
    Presentation's date: 2012-09-25
    Presentation of work at congresses

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    This paper explains the design decisions and the different measurements we have done in order to characterize the thermal coupling and the ch aracteristics of temperature sensors embedded in a integrated circuit implemented in a CMOS 65nm technology. The circu it contains a 2GHz linear power amplifier, MOS transistors behaving as heat sources and two differential temperatu re sensors. Temperature measurements performed with the embedded sensor are corroborated with an Infra-Red camera and a laser interferometer used as thermometer.

  • Impact of process variability and noise on the radiofrequency performance of carbon nanotube field-effect transistors

     Landauer, Gerhard Martin; Gonzalez Jimenez, Jose Luis
    NanoSpain Conference
    Presentation's date: 2012-02-27
    Presentation of work at congresses

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  • A 16-kV HBM RF ESD Protection Codesign for a 1-mW CMOS Direct Conversion Receiver Operating in the 2.4-GHz ISM Band

     Gonzalez Jimenez, Jose Luis; Solar, H.; Adin, Iñigo; Mateo Peña, Diego Cesar; Berenguer, Roc
    IEEE transactions on microwave theory and techniques
    Date of publication: 2011-09
    Journal article

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  • Design of a 2.5-GHZ QVCO robust against high frequency substrate noise

     Molina Garcia, Marc Manel; Gómez Salinas, Dídac; Aragones Cervera, Xavier; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Microwave and optical technology letters
    Date of publication: 2011-07
    Journal article

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    This work presents the design procedure followed to obtain a low-power voltage-controlled oscillator (VCO) robust against high-frequency substrate noise, using as a demonstrator a 2.5 GHz VCO with quadrature outputs (QVCO) based on a 5-GHz LC tank resonant VCO (LC-VCO) and frequency divider. A simple, intuitive, and easy to handle analytical model is proposed to identify the design parameters that contribute to the performance degradation of LC-VCOs due to the effect of high frequency substrate noise. The guidelines obtained have been applied in the design of the low-power QVCO. Finally, the work discusses several trade-offs that can be used to maximize the immunity of a LC-VCO against substrate noise.

  • THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 3: PA+Sensor layout integration and PVT analysis

     Martín, Mikel; Gonzalez Jimenez, Jose Luis
    Date: 2011-05-16
    Report

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    The objective is to detect the impact of PVT variations (Process, Voltage and Temperature variations) on the figures of merit of a device.

  • Inforrme de la segona anualitat del projecte CATRENE-PANAMA per al programa AVANZA I+D

     Gonzalez Jimenez, Jose Luis; Dufis, Cédric Yvan
    Date: 2011-03-16
    Report

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  • THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 1: Feasibility study

     Martin, Mikel; Gonzalez Jimenez, Jose Luis
    Date: 2011-03-02
    Report

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    In this Project, the verification of the possibility of extraction of information of a modulated signal through no-invasive thermal measurements is done. The main objective is that using a non-invasive thermal technique, information about the PA can be extracted so that the PA’s efficiency can be improved.

  • THERMAL OBSERVATION OF A MODULATED INPUT FOR A 2.5GHZ CMOS POWER AMPLIFIER Part 2: Temperature Sensor

     Martín, Mikel; Gonzalez Jimenez, Jose Luis
    Date: 2011-04-25
    Report

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    The temperature sensor used is based on the usual two bipolar transistors temperature sensor with some modifications to allow for external calibration (or “re-centering”).

  • A low-power impulse radio ultra-wideband transceiver for short-range, high-speed wireless communications

     Barajas Ojeda, Enrique
    Defense's date: 2011-08-29
    Department of Electronic Engineering, Universitat Politècnica de Catalunya
    Theses

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  • Non-invasive Monitoring of CMOS Power Amplifiers Operating at RF and mmW Frequencies using an On-chip Thermal Sensor

     Gonzalez Jimenez, Jose Luis; Martineau, Baudouin; Mateo Peña, Diego Cesar; Altet Sanahujes, Josep
    IEEE Radio Frequency Integrated Circuits Symposium
    Presentation's date: 2011-06-06
    Presentation of work at congresses

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    In this paper a non-invasive, contact-less technique for the on-chip observation of PA operation is presented. It uses a differential temperature sensor that transduces the temperature increase due to the power dissipated by active transistors operating at high frequencies into a low frequency signal that is proportional to some relevant PA figures of merit, such as output power or PAE. The technique is demonstrated by using the same thermal sensor in two different PAs (a 2 GHz PA and a 60 GHz PA) implemented with a 65 nm CMOS process.

  • SINTETIZADOR DE FRECUENCIA Y DIVISOR DE FRECUENCIA POR D BASADO EN LA TOPOLOGÍA DE ENG

     Brandano, Davide; Gonzalez Jimenez, Jose Luis
    Date of request: 2011-01-25
    Invention patent

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    Sintetizador de frecuencia y divisor de frecuencia por D basado en la topología de enganche por inyección.

    El sintetizador comprende:

    - un VCO (3), que proporciona una señal de salida con una frecuencia determinada (fVCO);

    - un ILFD (4), con una entrada conectada a la salida del VCO (3), y que proporciona, en condiciones de enganche, una señal con una frecuencia de enganche fVCO/D, siendo D un entero; y

    - un circuito de calibración de frecuencia (6) que genera y envía a unas entradas de control del VCO (3) y del ILFD (4) una o más señales de sintonización, para sintonizar, de manera simultánea, al VCO (3) a una curva de frecuencia determinada, y al ILFD (4) a una frecuencia de auto-resonancia determinada.

    El divisor de frecuencia por D basado en la topología de enganche por inyección, o ILFD, está adaptado para su inclusión en el sintetizador de frecuencia.

  • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

     Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio; Gonzalez Jimenez, Jose Luis; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Gonzalez Colas, Antonio Maria
    IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era
    Presentation's date: 2011-04-06
    Presentation of work at congresses

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    Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated costs, is studied for a Delay-Locked Loop design (DLL). The comparison with a full custom design demonstrates that VCTA can be used without loss of functionality while accelerating the design time. Layout implementations, in 90 nm CMOS process, as well as the delay, energy and jitter electrical simulations are provided.

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    A 56-GHz LC-Tank VCO With 17% tuning range in 65-nm bulk CMOS for wireless HDMI  Open access

     Gonzalez Jimenez, Jose Luis; Badets, Franck; Martineau, Baudouin; Belot, Didier
    IEEE transactions on microwave theory and techniques
    Date of publication: 2010-03-25
    Journal article

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    A voltage-controlled oscillator (VCO) with a central frequency of 56 GHz and a 17% tuning range is presented. The oscillation frequency is tuned both by an analog input and by a 3-bit digital control bus using the same type of differential varactors. It achieves a record figure of merit, considering tuning range of 186.8 dBc/Hz and is able to address the full wireless high-definition multimedia interface band . The VCO is implemented in a 65-nm bulk CMOS process and dissipates 15 mW from a 1.2-V supply. Both fixed and parameterized electromagnetic models for inductors, interconnection structures, and transmission lines have been embedded in the classical design flow including layout verification and extraction, resulting in a very high level of simulation accuracy.

  • POWER AMPLIFIERS AND ANTENNAS FOR MOBILE APPLICATIONS.APLICACIÓN AL HOME NETWORKING, Projecte Europeu CATRENE

     Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Dufis, Cédric Yvan; Gonzalez Jimenez, Jose Luis
    Participation in a competitive project

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  • Congresos Temperatura en Circuitos Integrados y Amplificadores de Potencia

     Rubio Sola, Jose Antonio; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Altet Sanahujes, Josep
    Participation in a competitive project

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  • CATRENE-PANAMA project review June 2010

     Gonzalez Jimenez, Jose Luis; Dufis, Cédric Yvan
    Date: 2010-06-03
    Report

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    Informe de progrés del projecte Europeu CATRENE-PANAMA sobre les tasques desenvolupades per el grup de recerca HiPICS de la UPC

  • CATRENE-PANAMA project review November 2010

     Gonzalez Jimenez, Jose Luis; Dufis, Cédric Yvan
    Date: 2010-11-23
    Report

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    Informe de progrés del projecte Europeu CATRENE-PANAMA sobre les tasques desenvolupades per el grup de recerca HiPICS de la UPC

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    A comparison between grounded and floating shield inductors for mmW VCOs  Open access

     Gonzalez Jimenez, Jose Luis; Aragones Cervera, Xavier; Molina Garcia, Marc Manel; Martineau, Baudouin; Belot, Didier
    European Solid-State Circuits Conference
    Presentation's date: 2010-09-15
    Presentation of work at congresses

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    A floating-shield inductor implemented in CMOS process is compared with a conventional patterned ground shield inductor for the implementation of a LC voltage controlled oscillator (VCO) operating at mmW frequencies. In this work it is shown how the floating-shield inductor achieves higher quality factor and provides a better isolation for substrate-coupled high-frequency interferences.

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    Providing an UWB-IR BAN wireless communications network and its application to design a low power transceiver in CMOS technology  Open access

     Barajas Ojeda, Enrique; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing
    Presentation's date: 2010-10-21
    Presentation of work at congresses

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    Ultra Wide-Band (UWB) communication techniques have received increasing attention since United States Federal Communications Commission (FCC) adopted a “First Report and Order” in 2002. Unfortunately the regulations that appeared a few years latter didn't have the same level of commitment and had much tighter constraints. The FCC part. 15 power spectral density limitation is depicted. Although the word-wide common bandwidth is quite scarce (7.25 to 8.5 GHz), UWB still has its niche applications. Impulse Radio (IR) implementation of UWB systems has very interesting features such as low complexity, low power consumption, low cost, high data-rate, and the ability of coexistence with other radio systems.

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    Effect of high frequency substrate noise on LC-VCOs  Open access

     Molina Garcia, Marc Manel; Aragones Cervera, Xavier; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    IEEE International Midwest Symposium on Circuits and Systems
    Presentation's date: 2010-08-03
    Presentation of work at congresses

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    This paper presents an experimental analysis of the performance degradation of an LC-Voltage Controlled Oscillator (LC-VCO) produced by high frequency noise present in the substrate. The spurs observed are shown to be caused by a frequency pulling mechanism. Based on the theory of injection locked oscillators, a new analytical model to predict the behavior of the LC-VCO under the effect of high frequency substrate noise is presented. The analytical model, which is successfully compared with experimental measurements on a 7 GHz LCVCO, provides rapid intuition on the relation between spurs and circuit parameters.

  • Design of Frequency Divider in 65 nm CMOS Technology for a short range millimeter-wave direct-conversion transceiver for WHDMI applications

     Brandano, Davide; Gonzalez Jimenez, Jose Luis
    Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing
    Presentation's date: 2010-10-21
    Presentation of work at congresses

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  • Design of Injection-Locked Frequency Divider in 65 nm CMOS Technology for mm-W applications

     Brandano, Davide; Gonzalez Jimenez, Jose Luis
    European Solid-State Circuits Conference
    Presentation's date: 2010-09-14
    Presentation of work at congresses

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  • Design of a wideband class-A power amplifier for wireline communication

     Dufis, Cédric Yvan; Gonzalez Jimenez, Jose Luis
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2010-11-17
    Presentation of work at congresses

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    This paper introduce a design review of a wideband Power Amplifier with a 65nm CMOS technology. The Integrated Circuit has to work from 300MHz to 2:5GHz with external components adapted to a specific band. A 2.5D simulation of the QFN24 is lead to evaluate the parasitic effects generated by the package. The one and two tones analysis are performed to characterize the PA. The 1dB Compression Point reach 10:36dBm and the Output referred Third order Interception Point is 23:98dBm. The Power Added Efficiency reached at the 1dB Compression Point is around 11:5% including the effect of the external components and the post-layout parasitics of the Integrated Circuit.

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    On evaluating temperature as observable for CMOS technology variability  Open access

     Altet Sanahujes, Josep; Gómez Salinas, Dídac; Dufis, Cédric Yvan; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Moll Echeto, Francesc de Borja; Rubio Sola, Jose Antonio
    European workshop on CMOS Variability
    Presentation's date: 2010-05-26
    Presentation of work at congresses

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    The temperature at surface of a silicon die depends on the activity of the circuits placed on it. In this paper, it is analyzed how Process, Voltage and Temperature (PVT) variations affect simultaneously some figures of merit (FoM) of some digital and analog circuits and the power dissipated by such circuits. It is shown that in some cases, a strong correlation exists between the variation of the circuit FoM and the variation of the dissipated power. Since local temperature increase at the silicon surface close to the circuit linearly depends on dissipated power, the results show that temperature can be considered as an observable magnitude for CMOS technology variability monitoring.

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    DLL's behavioral modeling for power consumption and jitter fast optimization  Open access

     Barajas Ojeda, Enrique; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2010-11-18
    Presentation of work at congresses

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    This paper analyzes the sources of jitter in a DLL and presents a behavioral model for fast DLL optimization. An algorithm to simulate the DLL in open loop is demonstrated. This procedure, together with the behavioral modeling, greatly reduces the simulation time of DLL when compared to the closeloop DLL simulation. In order to optimize the DLL performance, the dependence of the output jitter versus the power consumption is studied.

    Postprint (author’s final draft)

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    Design of injection locked frequency divider in 65nm CMOS technology for mmW applications  Open access

     Brandano, Davide; Gonzalez Jimenez, Jose Luis
    Conference on Design of Circuits and Integrated Systems
    Presentation's date: 2010-09-15
    Presentation of work at congresses

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    In this paper, an Injection Locking Frequency Divider (ILFD) in 65 nm RF CMOS Technology for applications in millimeter-wave (mm-W) band is presented. The proposed circuit achieves 12.69% of locking range without any tuning mechanism and it can cover the entire mm-W band in presence of Process, Voltage and Temperature (PVT) variations by changing the Injection Locking Oscillator (ILO) voltage control. A design methodology flow is proposed for ILFD design and an overview regarding CMOS capabilities and opportunities for mm-W transceiver implementation is also exposed.

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    A 75 pJ/bit all-digital quadrature coherent IR-UWB transceiver in 0.18 um CMOS  Open access

     Barajas Ojeda, Enrique; Gómez Salinas, Dídac; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    IEEE Radio Frequency Integrated Circuits Symposium
    Presentation's date: 2010-05-24
    Presentation of work at congresses

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    In this paper a 75 pJ/b all-digital quadrature coherent impulse radio ultra-wideband transceiver in 0.18 μm CMOS is presented. It consumes 42 mW operating at a 560 Mbps datarate. The receiver and transmitter share most of the components reducing the area. This design is optimal for low-power low-cost short-range high-speed communications.

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    Behavioural modelling of DLLs for fast simulation and optimisation of jitter and power consumption  Open access

     Barajas Ojeda, Enrique; Mateo Peña, Diego Cesar; Gonzalez Jimenez, Jose Luis
    Euromicro Symposium on Digital Systems Design
    Presentation's date: 2010-09-02
    Presentation of work at congresses

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    This paper presents a behavioural model for fast DLL simulations. The behavioural model includes a modelling of the various noise sources in the DLL that produce output jitter. The model is used to obtain the dependence of the output jitter versus the power consumption. The model exploits the open-loop DLL analysis to reduce simulation time when compared to typical DLL evaluation.

  • A 56GHz LC-Tank VCO with 17% Tuning Range in 65nm Bulk CMOS for Wireless HDMI Applications

     Gonzalez Jimenez, Jose Luis; Badets, Franck; Martineau, Baudouin; Belot, Didier
    Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE
    Date of publication: 2009
    Journal article

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    Process and temperature compensation for RF low-noise amplifiers and mixers  Open access

     Gómez Salinas, Didac; Sroka, Milosz; Gonzalez Jimenez, Jose Luis
    IEEE transactions on circuits and systems I: regular papers
    Date of publication: 2009-12-18
    Journal article

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    Temperature and process variations have become key issues in the design of integrated circuits using deep submicron technologies. In RF front-end circuitry, many characteristics must be compensated in order to maintain acceptable performance across all process corners and throughout the temperature range. This paper proposes a new technique consisting of a compensation circuit that adapts and generates the appropriate bias voltage for LNAs and mixers so that the variability with temperature and process corners of their main performance metrics (S-parameters, gain, noise figure, etc.) is minimized.

  • Design And Test Principles For Terascale Integrated Systems

     Rubio Sola, Jose Antonio; Altet Sanahujes, Josep; Aragones Cervera, Xavier; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Calomarde Palomino, Antonio; García Leyva, Lancelot; Andrade Miceli, Dennis Michael
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  • Modeling and design of reliable, process-variation aware nanoelectronic devices,circuits and systems

     Pons Solé, Marc; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Perez Puigdemont, Jordi; Mauricio Ferré, Juan; Gómez Salinas, Dídac; García Leyva, Lancelot; Gonzalez Jimenez, Jose Luis; Altet Sanahujes, Josep; Moll Echeto, Francesc de Borja
    Participation in a competitive project

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  • Modeling and design of reliable, process-variation aware nanoelectronic devices,circuits and systems

     Aragones Cervera, Xavier; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Perez Puigdemont, Jordi; Mauricio Ferré, Juan; Gómez Salinas, Dídac; García Leyva, Lancelot; Gonzalez Jimenez, Jose Luis; Altet Sanahujes, Josep; Pons Solé, Marc; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja
    Participation in a competitive project

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  • Experimental Analysis of Substrate Isolation TEchniques for RF-SoC Integration

     Molina, Marc Garcia; Aragones Cervera, Xavier; Gonzalez Jimenez, Jose Luis
    International Symposium on System-on-Chip
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  • POWER AMPLIFIERS AND ANTENNAS FOR MOBILE APPLICATIONS.APLICACIÓN AL HOME NETWORKING, Projecte Europeu CATRENE

     Altet Sanahujes, Josep; Mateo Peña, Diego Cesar; Dufis, Cédric Yvan; Gonzalez Jimenez, Jose Luis
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  • CIMHOGAR 2: CONECTIVIDAD INTEGRAL MULTIMEDIA EN EL HOGAR

     Trulls Fortuny, Xavier; Mateo Peña, Diego Cesar; Molina Garcia, Marc Manel; Gonzalez Jimenez, Jose Luis
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  • GRUP DE RECERCA DE CIRCUITS I SISTEMES INTEGRATS D'ALTES PRESTACIONS (HIPICS)

     Rubio Sola, Jose Antonio; Mateo Peña, Diego Cesar; Moll Echeto, Francesc de Borja; Gonzalez Jimenez, Jose Luis; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Molina Garcia, Marc Manel; Barajas Ojeda, Enrique; Gómez Salinas, Dídac; García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Pons Solé, Marc; Trulls Fortuny, Xavier; Dufis, Cédric Yvan; Landauer, Gerhard Martin; Garcia Almudever, Carmen; Perez Puigdemont, Jordi; Aymerich Capdevila, Nivard; Gomez Fernandez, Sergio; Aragones Cervera, Xavier
    Participation in a competitive project

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  • Substrate noise interference in RF integrated circuits

     Gonzalez Jimenez, Jose Luis
    IEEE International Microwave Symposium
    Presentation of work at congresses

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  • A 56 GHzLC-Tank VCO with 17% tuning range in 65nm bulk CMOS for wireless HDMI applications

     Gonzalez Jimenez, Jose Luis; Franck, Badets; Martineau, Baudouin; Didier, Belot
    2009 IEEE Radio Frequency Integrated Circuits Symposium
    Presentation of work at congresses

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  • A Process and Temperature Compensation Technique for RF Low-Noise Amplifiers and Mixers

     Milosz, Sroka; Gonzalez Jimenez, Jose Luis; Didac, Gómez; Aragones Cervera, Xavier; Mateo Peña, Diego Cesar; Molina, Marc
    Conference on Design of Circuits and Integrated Systems
    Presentation of work at congresses

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  • Ultra low power QVCO for the 2.5 GHz ISM band using a 5GHz LC VCO with a frequency divider

     Molina, Marc; Didac, Gómez; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier
    Conference on Design of Circuits and Integrated Systems
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  • A Low-Power RF Front-End for 2.5 GHz Receivers

     Moreno, L; Gómez, D; Gonzalez Jimenez, Jose Luis; Mateo Peña, Diego Cesar; Aragones Cervera, Xavier; Berenguer, R; Solar, H
    IEEE International Symposium on Circuits and Systems
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